gfni.h

// SPDX-FileCopyrightText: 2026 Edward Kmett <ekmett@gmail.com>
// SPDX-License-Identifier: BSD-2-Clause OR Apache-2.0
#pragma once
#include "native/config.h"
#include "native/attributes.h"
#include "native/isa.h"
#if NATIVE_HOST_X86
#include <immintrin.h>
#endif
 
#if NATIVE_HOST_X86 || defined(NATIVE_DOXYGEN)
namespace native::detail::x86_gfni {
// Internal register helpers for the native.x86.gfni module.
 
 
  // 128-bit registers.
  template<isa<x86> Arch> requires(Arch.has(x86_feature::gfni))
  native_nodiscard native_inline native_const native_target("gfni")
  __m128i gf2p8mulb(__m128i a, __m128i b) noexcept {
    return _mm_gf2p8mul_epi8(a, b);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("gfni")
  __m128i gf2p8affineqb(__m128i a, __m128i matrix) noexcept {
    return _mm_gf2p8affine_epi64_epi8(a, matrix, Imm8);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("gfni")
  __m128i gf2p8affineinvqb(__m128i a, __m128i matrix) noexcept {
    return _mm_gf2p8affineinv_epi64_epi8(a, matrix, Imm8);
  }

  template<isa<x86> Arch> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))
  native_nodiscard native_inline native_const native_target("avx512bw,avx512vl,gfni")
  __m128i gf2p8mulb_mask(__m128i src, __mmask16 k, __m128i a, __m128i b) noexcept {
    return _mm_mask_gf2p8mul_epi8(src, k, a, b);
  }

  template<isa<x86> Arch> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))
  native_nodiscard native_inline native_const native_target("avx512bw,avx512vl,gfni")
  __m128i gf2p8mulb_maskz(__mmask16 k, __m128i a, __m128i b) noexcept {
    return _mm_maskz_gf2p8mul_epi8(k, a, b);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("avx512bw,avx512vl,gfni")
  __m128i gf2p8affineqb_mask(__m128i src, __mmask16 k, __m128i a, __m128i matrix) noexcept {
    return _mm_mask_gf2p8affine_epi64_epi8(src, k, a, matrix, Imm8);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("avx512bw,avx512vl,gfni")
  __m128i gf2p8affineqb_maskz(__mmask16 k, __m128i a, __m128i matrix) noexcept {
    return _mm_maskz_gf2p8affine_epi64_epi8(k, a, matrix, Imm8);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("avx512bw,avx512vl,gfni")
  __m128i gf2p8affineinvqb_mask(__m128i src, __mmask16 k, __m128i a, __m128i matrix) noexcept {
    return _mm_mask_gf2p8affineinv_epi64_epi8(src, k, a, matrix, Imm8);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("avx512bw,avx512vl,gfni")
  __m128i gf2p8affineinvqb_maskz(__mmask16 k, __m128i a, __m128i matrix) noexcept {
    return _mm_maskz_gf2p8affineinv_epi64_epi8(k, a, matrix, Imm8);
  }
 
 
  // 256-bit registers.
  template<isa<x86> Arch> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx))
  native_nodiscard native_inline native_const native_target("avx,gfni")
  __m256i gf2p8mulb(__m256i a, __m256i b) noexcept {
    return _mm256_gf2p8mul_epi8(a, b);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("avx,gfni")
  __m256i gf2p8affineqb(__m256i a, __m256i matrix) noexcept {
    return _mm256_gf2p8affine_epi64_epi8(a, matrix, Imm8);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("avx,gfni")
  __m256i gf2p8affineinvqb(__m256i a, __m256i matrix) noexcept {
    return _mm256_gf2p8affineinv_epi64_epi8(a, matrix, Imm8);
  }

  template<isa<x86> Arch> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))
  native_nodiscard native_inline native_const native_target("avx512bw,avx512vl,gfni")
  __m256i gf2p8mulb_mask(__m256i src, __mmask32 k, __m256i a, __m256i b) noexcept {
    return _mm256_mask_gf2p8mul_epi8(src, k, a, b);
  }

  template<isa<x86> Arch> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))
  native_nodiscard native_inline native_const native_target("avx512bw,avx512vl,gfni")
  __m256i gf2p8mulb_maskz(__mmask32 k, __m256i a, __m256i b) noexcept {
    return _mm256_maskz_gf2p8mul_epi8(k, a, b);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("avx512bw,avx512vl,gfni")
  __m256i gf2p8affineqb_mask(__m256i src, __mmask32 k, __m256i a, __m256i matrix) noexcept {
    return _mm256_mask_gf2p8affine_epi64_epi8(src, k, a, matrix, Imm8);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("avx512bw,avx512vl,gfni")
  __m256i gf2p8affineqb_maskz(__mmask32 k, __m256i a, __m256i matrix) noexcept {
    return _mm256_maskz_gf2p8affine_epi64_epi8(k, a, matrix, Imm8);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("avx512bw,avx512vl,gfni")
  __m256i gf2p8affineinvqb_mask(__m256i src, __mmask32 k, __m256i a, __m256i matrix) noexcept {
    return _mm256_mask_gf2p8affineinv_epi64_epi8(src, k, a, matrix, Imm8);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("avx512bw,avx512vl,gfni")
  __m256i gf2p8affineinvqb_maskz(__mmask32 k, __m256i a, __m256i matrix) noexcept {
    return _mm256_maskz_gf2p8affineinv_epi64_epi8(k, a, matrix, Imm8);
  }
 
 
  // 512-bit registers.
  template<isa<x86> Arch> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f))
  native_nodiscard native_inline native_const native_target("avx512f,gfni")
  __m512i gf2p8mulb(__m512i a, __m512i b) noexcept {
    return _mm512_gf2p8mul_epi8(a, b);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("avx512f,gfni")
  __m512i gf2p8affineqb(__m512i a, __m512i matrix) noexcept {
    return _mm512_gf2p8affine_epi64_epi8(a, matrix, Imm8);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("avx512f,gfni")
  __m512i gf2p8affineinvqb(__m512i a, __m512i matrix) noexcept {
    return _mm512_gf2p8affineinv_epi64_epi8(a, matrix, Imm8);
  }

  template<isa<x86> Arch> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw))
  native_nodiscard native_inline native_const native_target("avx512bw,gfni")
  __m512i gf2p8mulb_mask(__m512i src, __mmask64 k, __m512i a, __m512i b) noexcept {
    return _mm512_mask_gf2p8mul_epi8(src, k, a, b);
  }

  template<isa<x86> Arch> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw))
  native_nodiscard native_inline native_const native_target("avx512bw,gfni")
  __m512i gf2p8mulb_maskz(__mmask64 k, __m512i a, __m512i b) noexcept {
    return _mm512_maskz_gf2p8mul_epi8(k, a, b);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("avx512bw,gfni")
  __m512i gf2p8affineqb_mask(__m512i src, __mmask64 k, __m512i a, __m512i matrix) noexcept {
    return _mm512_mask_gf2p8affine_epi64_epi8(src, k, a, matrix, Imm8);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("avx512bw,gfni")
  __m512i gf2p8affineqb_maskz(__mmask64 k, __m512i a, __m512i matrix) noexcept {
    return _mm512_maskz_gf2p8affine_epi64_epi8(k, a, matrix, Imm8);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("avx512bw,gfni")
  __m512i gf2p8affineinvqb_mask(__m512i src, __mmask64 k, __m512i a, __m512i matrix) noexcept {
    return _mm512_mask_gf2p8affineinv_epi64_epi8(src, k, a, matrix, Imm8);
  }

  template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) &&
      Arch.has(x86_feature::avx512bw) && Imm8 <= 255)
  native_nodiscard native_inline native_const native_target("avx512bw,gfni")
  __m512i gf2p8affineinvqb_maskz(__mmask64 k, __m512i a, __m512i matrix) noexcept {
    return _mm512_maskz_gf2p8affineinv_epi64_epi8(k, a, matrix, Imm8);
  }
 
 
}
#endif