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Vectors, masks and wide register packs for C++26
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targets.h
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// SPDX-FileCopyrightText: 2026 Edward Kmett <ekmett@gmail.com>
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// SPDX-License-Identifier: BSD-2-Clause OR Apache-2.0
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#pragma once
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// Textual macros only: this header can precede or follow `import native;`.
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// Its expansions require the exported native ISA metadata. Clang is intentional.
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#ifndef __clang__
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#error native source target variants require Clang
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#endif
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// Register a custom source name with one literal, for example:
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// #define NATIVE_TARGET_compact "avx2,f16c"
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// The same literal drives compiler attributes, ISA values and admission.
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// Only positive feature names in native's registry are accepted; CPU names and
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// arbitrary C++ aliases cannot be reverse-engineered into compiler attributes.
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// The empty literal gives scalar metadata; its scope below deliberately applies
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// no target attribute. Clang reserves "default" for function multiversioning.
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#define NATIVE_TARGET_scalar ""
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#define NATIVE_TARGET_avx2 "avx2,fma"
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#define NATIVE_TARGET_avx512 "avx2,fma,avx512f,avx512dq,avx512bw,avx512vl"
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#define NATIVE_TARGET_avx512_bf16 "avx2,fma,avx512f,avx512dq,avx512bw,avx512vl,avx512bf16"
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#define NATIVE_TARGET_avx512_fp16 "avx2,fma,avx512f,avx512dq,avx512bw,avx512vl,avx512fp16"
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#define NATIVE_TARGET_neon "neon"
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#define NATIVE_TARGET_neon_fp16 "neon,fullfp16"
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#define NATIVE_TARGET_neon_bf16 "neon,bf16"
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#define NATIVE_DETAIL_TARGET_CAT_I(a,b) a##b
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#define NATIVE_DETAIL_TARGET_CAT(a,b) NATIVE_DETAIL_TARGET_CAT_I(a,b)
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#define NATIVE_DETAIL_TARGET_STRING_I(...) #__VA_ARGS__
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#define NATIVE_DETAIL_TARGET_STRING(...) NATIVE_DETAIL_TARGET_STRING_I(__VA_ARGS__)
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#define NATIVE_DETAIL_TARGET_PRAGMA(...) _Pragma(NATIVE_DETAIL_TARGET_STRING(__VA_ARGS__))
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#define NATIVE_TARGET_STRING(name) NATIVE_DETAIL_TARGET_CAT(NATIVE_TARGET_,name)
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#define NATIVE_TARGET_ISA(name) \
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(::native::detail::source_isa<::native::target_features(NATIVE_TARGET_STRING(name))>)
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// The named pragma stack prevents accidentally popping an unrelated user's
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// clang attribute stack. This does not generate preprocessor #include lines.
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// Generate outside other ISA target scopes: Clang combines nested requirements,
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// which predefines cannot observe. Intentional nesting must record the outer
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// requirements in NATIVE_TARGET_EXTRA_MINIMUM for admission.
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#define NATIVE_DETAIL_TARGET_SECOND(a,b,...) b
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#define NATIVE_DETAIL_TARGET_PROBE() unused,1
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#define NATIVE_DETAIL_TARGET_SCALAR_scalar NATIVE_DETAIL_TARGET_PROBE()
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#define NATIVE_DETAIL_TARGET_IS_SCALAR_I(...) NATIVE_DETAIL_TARGET_SECOND(__VA_ARGS__,0)
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#define NATIVE_DETAIL_TARGET_IS_SCALAR(name) \
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NATIVE_DETAIL_TARGET_IS_SCALAR_I(NATIVE_DETAIL_TARGET_CAT(NATIVE_DETAIL_TARGET_SCALAR_,name))
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#define NATIVE_DETAIL_TARGET_PUSH_0(name) \
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NATIVE_DETAIL_TARGET_PRAGMA(clang attribute native_source_target.push(__attribute__((target(NATIVE_TARGET_STRING(name)))), apply_to=function))
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#define NATIVE_DETAIL_TARGET_PUSH_1(name) \
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NATIVE_DETAIL_TARGET_PRAGMA(clang attribute native_source_target.push)
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#define NATIVE_TARGET_PUSH(name) \
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NATIVE_DETAIL_TARGET_CAT(NATIVE_DETAIL_TARGET_PUSH_,NATIVE_DETAIL_TARGET_IS_SCALAR(name))(name)
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#define NATIVE_TARGET_POP() NATIVE_DETAIL_TARGET_PRAGMA(clang attribute native_source_target.pop)
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/*
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Context-aware adaptation of BAD_MAP in
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https://github.com/ekmett/bad/blob/main/include/bad/macros.hh
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Copyright (C) 2012 William Swanson, 2021 Edward Kmett.
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Permission is hereby granted, free of charge, to any person obtaining a copy of
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this software and associated documentation files (the "Software"), to deal in
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the Software without restriction, including without limitation the rights to
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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the Software, and to permit persons to whom the Software is furnished to do so,
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subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the names of the authors or their
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institutions shall not be used in advertising or otherwise to promote the sale,
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use or other dealings in this Software without prior written authorization from
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the authors.
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*/
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#define NATIVE_DETAIL_TARGET_EVAL0(...) __VA_ARGS__
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#define NATIVE_DETAIL_TARGET_EVAL1(...) NATIVE_DETAIL_TARGET_EVAL0(NATIVE_DETAIL_TARGET_EVAL0(NATIVE_DETAIL_TARGET_EVAL0(__VA_ARGS__)))
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#define NATIVE_DETAIL_TARGET_EVAL2(...) NATIVE_DETAIL_TARGET_EVAL1(NATIVE_DETAIL_TARGET_EVAL1(NATIVE_DETAIL_TARGET_EVAL1(__VA_ARGS__)))
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#define NATIVE_DETAIL_TARGET_EVAL3(...) NATIVE_DETAIL_TARGET_EVAL2(NATIVE_DETAIL_TARGET_EVAL2(NATIVE_DETAIL_TARGET_EVAL2(__VA_ARGS__)))
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#define NATIVE_DETAIL_TARGET_EVAL4(...) NATIVE_DETAIL_TARGET_EVAL3(NATIVE_DETAIL_TARGET_EVAL3(NATIVE_DETAIL_TARGET_EVAL3(__VA_ARGS__)))
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#define NATIVE_DETAIL_TARGET_EVAL(...) NATIVE_DETAIL_TARGET_EVAL4(NATIVE_DETAIL_TARGET_EVAL4(NATIVE_DETAIL_TARGET_EVAL4(__VA_ARGS__)))
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#define NATIVE_DETAIL_TARGET_MAP_END(...)
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#define NATIVE_DETAIL_TARGET_MAP_OUT
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#define NATIVE_DETAIL_TARGET_MAP_GET_END2() 0, NATIVE_DETAIL_TARGET_MAP_END
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#define NATIVE_DETAIL_TARGET_MAP_GET_END1(...) NATIVE_DETAIL_TARGET_MAP_GET_END2
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#define NATIVE_DETAIL_TARGET_MAP_GET_END(...) NATIVE_DETAIL_TARGET_MAP_GET_END1
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#define NATIVE_DETAIL_TARGET_MAP_NEXT0(test, next, ...) next NATIVE_DETAIL_TARGET_MAP_OUT
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#define NATIVE_DETAIL_TARGET_MAP_NEXT1(test, next) NATIVE_DETAIL_TARGET_MAP_NEXT0(test, next, 0)
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#define NATIVE_DETAIL_TARGET_MAP_NEXT(test, next) NATIVE_DETAIL_TARGET_MAP_NEXT1(NATIVE_DETAIL_TARGET_MAP_GET_END test, next)
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#define NATIVE_DETAIL_TARGET_MAP0(f,c,x,peek,...) f(c,x) NATIVE_DETAIL_TARGET_MAP_NEXT(peek,NATIVE_DETAIL_TARGET_MAP1)(f,c,peek,__VA_ARGS__)
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#define NATIVE_DETAIL_TARGET_MAP1(f,c,x,peek,...) f(c,x) NATIVE_DETAIL_TARGET_MAP_NEXT(peek,NATIVE_DETAIL_TARGET_MAP0)(f,c,peek,__VA_ARGS__)
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#define NATIVE_DETAIL_TARGET_MAP(f,c,...) __VA_OPT__(NATIVE_DETAIL_TARGET_EVAL(NATIVE_DETAIL_TARGET_MAP1(f,c,__VA_ARGS__,()()(),()()(),()()(),0)))
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#define NATIVE_DETAIL_TARGET_UNPACK(...) __VA_ARGS__
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#define NATIVE_DETAIL_TARGET_ISA_ARG(unused,tag) ,NATIVE_TARGET_ISA(tag)
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// A list is a comma-separated sequence of registered target names:
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// #define targets avx512,avx2
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// body(name,ISA,...) receives the selected ISA followed by the full ISA pack.
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// Use target<A,__VA_ARGS__> == target<ISA,__VA_ARGS__> for disjoint overloads.
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// Keep local register types and instruction requirements within ISA, even when
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// A carries more features. Definitions need normal C++ ODR rules.
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// Expand the complete choice pack before mapping bodies, keeping the two uses
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// of the mapper separate during preprocessor rescanning.
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#define NATIVE_TARGET_VARIANTS(name,body,...) NATIVE_DETAIL_TARGET_VARIANTS(name,body,__VA_ARGS__)
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#define NATIVE_DETAIL_TARGET_VARIANTS(name,body,...) \
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NATIVE_DETAIL_TARGET_EMIT_ALL(name,body, \
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(NATIVE_DETAIL_TARGET_MAP(NATIVE_DETAIL_TARGET_ISA_ARG,unused,__VA_ARGS__)),__VA_ARGS__)
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#define NATIVE_DETAIL_TARGET_EMIT_ALL(name,body,choices,...) \
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NATIVE_DETAIL_TARGET_MAP(NATIVE_DETAIL_TARGET_EMIT,(name,body,choices),__VA_ARGS__)
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#define NATIVE_DETAIL_TARGET_EMIT(context,tag) \
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NATIVE_DETAIL_TARGET_EMIT_EXPAND(tag,NATIVE_DETAIL_TARGET_UNPACK context)
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#define NATIVE_DETAIL_TARGET_EMIT_EXPAND(...) NATIVE_DETAIL_TARGET_EMIT_IMPL(__VA_ARGS__)
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#define NATIVE_DETAIL_TARGET_EMIT_IMPL(tag,name,body,choices) \
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NATIVE_TARGET_PUSH(tag) \
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NATIVE_DETAIL_TARGET_EMIT_BODY(body,name,NATIVE_TARGET_ISA(tag) NATIVE_DETAIL_TARGET_UNPACK choices) \
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NATIVE_TARGET_POP()
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#define NATIVE_DETAIL_TARGET_EMIT_BODY(body,...) body(__VA_ARGS__)
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// Snapshot inherited translation-unit features separately from the requested
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// ISA value. A target attribute adds features; it does not erase the project
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// minimum. An unregistered stronger minimum is rejected instead of under-admitted.
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#ifdef __MMX__
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#define NATIVE_DETAIL_MIN_MMX (::native::isa<>(::native::x86_feature::mmx))
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#else
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#define NATIVE_DETAIL_MIN_MMX (::native::isa<>{})
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#endif
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#ifdef __SSE__
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#define NATIVE_DETAIL_MIN_SSE (::native::isa<>(::native::x86_feature::sse))
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#else
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#define NATIVE_DETAIL_MIN_SSE (::native::isa<>{})
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#endif
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#ifdef __SSE2__
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#define NATIVE_DETAIL_MIN_SSE2 (::native::isa<>(::native::x86_feature::sse2))
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#else
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#define NATIVE_DETAIL_MIN_SSE2 (::native::isa<>{})
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#endif
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#ifdef __SSE3__
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#define NATIVE_DETAIL_MIN_SSE3 (::native::isa<>(::native::x86_feature::sse3))
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#else
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#define NATIVE_DETAIL_MIN_SSE3 (::native::isa<>{})
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#endif
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#ifdef __SSSE3__
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#define NATIVE_DETAIL_MIN_SSSE3 (::native::isa<>(::native::x86_feature::ssse3))
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#else
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#define NATIVE_DETAIL_MIN_SSSE3 (::native::isa<>{})
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#endif
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#ifdef __SSE4_1__
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#define NATIVE_DETAIL_MIN_SSE41 (::native::isa<>(::native::x86_feature::sse41))
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#else
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#define NATIVE_DETAIL_MIN_SSE41 (::native::isa<>{})
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#endif
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#ifdef __SSE4_2__
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#define NATIVE_DETAIL_MIN_SSE42 (::native::isa<>(::native::x86_feature::sse42))
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#else
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#define NATIVE_DETAIL_MIN_SSE42 (::native::isa<>{})
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#endif
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#ifdef __POPCNT__
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#define NATIVE_DETAIL_MIN_POPCNT (::native::isa<>(::native::x86_feature::popcnt))
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#else
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#define NATIVE_DETAIL_MIN_POPCNT (::native::isa<>{})
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#endif
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#ifdef __AVX__
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#define NATIVE_DETAIL_MIN_AVX (::native::isa<>(::native::x86_feature::avx))
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#else
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#define NATIVE_DETAIL_MIN_AVX (::native::isa<>{})
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#endif
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#ifdef __AVX2__
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#define NATIVE_DETAIL_MIN_AVX2 (::native::isa<>(::native::x86_feature::avx2))
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#else
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#define NATIVE_DETAIL_MIN_AVX2 (::native::isa<>{})
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#endif
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#ifdef __FMA__
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#define NATIVE_DETAIL_MIN_FMA (::native::isa<>(::native::x86_feature::fma))
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#else
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#define NATIVE_DETAIL_MIN_FMA (::native::isa<>{})
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#endif
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#ifdef __F16C__
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#define NATIVE_DETAIL_MIN_F16C (::native::isa<>(::native::x86_feature::f16c))
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#else
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#define NATIVE_DETAIL_MIN_F16C (::native::isa<>{})
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#endif
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#ifdef __BMI__
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#define NATIVE_DETAIL_MIN_BMI1 (::native::isa<>(::native::x86_feature::bmi1))
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#else
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#define NATIVE_DETAIL_MIN_BMI1 (::native::isa<>{})
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#endif
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#ifdef __BMI2__
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#define NATIVE_DETAIL_MIN_BMI2 (::native::isa<>(::native::x86_feature::bmi2))
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#else
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#define NATIVE_DETAIL_MIN_BMI2 (::native::isa<>{})
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#endif
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#ifdef __AVX512F__
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#define NATIVE_DETAIL_MIN_AVX512F (::native::isa<>(::native::x86_feature::avx512f))
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#else
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#define NATIVE_DETAIL_MIN_AVX512F (::native::isa<>{})
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#endif
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#ifdef __AVX512DQ__
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#define NATIVE_DETAIL_MIN_AVX512DQ (::native::isa<>(::native::x86_feature::avx512dq))
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#else
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#define NATIVE_DETAIL_MIN_AVX512DQ (::native::isa<>{})
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#endif
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#ifdef __AVX512BW__
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#define NATIVE_DETAIL_MIN_AVX512BW (::native::isa<>(::native::x86_feature::avx512bw))
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#else
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#define NATIVE_DETAIL_MIN_AVX512BW (::native::isa<>{})
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#endif
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#ifdef __AVX512VL__
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#define NATIVE_DETAIL_MIN_AVX512VL (::native::isa<>(::native::x86_feature::avx512vl))
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#else
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#define NATIVE_DETAIL_MIN_AVX512VL (::native::isa<>{})
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#endif
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#ifdef __AVX512BF16__
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#define NATIVE_DETAIL_MIN_AVX512BF16 (::native::isa<>(::native::x86_feature::avx512bf16))
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#else
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#define NATIVE_DETAIL_MIN_AVX512BF16 (::native::isa<>{})
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#endif
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#ifdef __AVX512FP16__
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#define NATIVE_DETAIL_MIN_AVX512FP16 (::native::isa<>(::native::x86_feature::avx512fp16))
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#else
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#define NATIVE_DETAIL_MIN_AVX512FP16 (::native::isa<>{})
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#endif
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#ifdef __AVX512VBMI__
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#define NATIVE_DETAIL_MIN_AVX512VBMI (::native::isa<>(::native::x86_feature::avx512vbmi))
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#else
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#define NATIVE_DETAIL_MIN_AVX512VBMI (::native::isa<>{})
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#endif
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#ifdef __AVX512VBMI2__
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#define NATIVE_DETAIL_MIN_AVX512VBMI2 (::native::isa<>(::native::x86_feature::avx512vbmi2))
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#else
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#define NATIVE_DETAIL_MIN_AVX512VBMI2 (::native::isa<>{})
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#endif
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#ifdef __AVX512BITALG__
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#define NATIVE_DETAIL_MIN_AVX512BITALG (::native::isa<>(::native::x86_feature::avx512bitalg))
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#else
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#define NATIVE_DETAIL_MIN_AVX512BITALG (::native::isa<>{})
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#endif
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#ifdef __AVX512VPOPCNTDQ__
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#define NATIVE_DETAIL_MIN_AVX512VPOPCNTDQ (::native::isa<>(::native::x86_feature::avx512vpopcntdq))
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#else
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#define NATIVE_DETAIL_MIN_AVX512VPOPCNTDQ (::native::isa<>{})
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#endif
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#ifdef __AVXVNNI__
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#define NATIVE_DETAIL_MIN_AVXVNNI (::native::isa<>(::native::x86_feature::avxvnni))
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#else
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#define NATIVE_DETAIL_MIN_AVXVNNI (::native::isa<>{})
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#endif
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#ifdef __AVX512VNNI__
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#define NATIVE_DETAIL_MIN_AVX512VNNI (::native::isa<>(::native::x86_feature::avx512vnni))
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#else
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#define NATIVE_DETAIL_MIN_AVX512VNNI (::native::isa<>{})
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#endif
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#ifdef __AVXVNNIINT8__
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#define NATIVE_DETAIL_MIN_AVXVNNIINT8 (::native::isa<>(::native::x86_feature::avxvnniint8))
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#else
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#define NATIVE_DETAIL_MIN_AVXVNNIINT8 (::native::isa<>{})
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#endif
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#ifdef __AVXVNNIINT16__
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#define NATIVE_DETAIL_MIN_AVXVNNIINT16 (::native::isa<>(::native::x86_feature::avxvnniint16))
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#else
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#define NATIVE_DETAIL_MIN_AVXVNNIINT16 (::native::isa<>{})
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#endif
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#ifdef __ARM_NEON
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#define NATIVE_DETAIL_MIN_NEON (::native::isa<>(::native::arm_feature::neon))
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#else
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#define NATIVE_DETAIL_MIN_NEON (::native::isa<>{})
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#endif
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#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) || defined(__ARM_FEATURE_FP16_SCALAR_ARITHMETIC)
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#define NATIVE_DETAIL_MIN_NEON_FP16 (::native::isa<>(::native::arm_feature::neon_fp16))
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#else
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#define NATIVE_DETAIL_MIN_NEON_FP16 (::native::isa<>{})
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#endif
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#ifdef __ARM_FEATURE_BF16_VECTOR_ARITHMETIC
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#define NATIVE_DETAIL_MIN_NEON_BF16 (::native::isa<>(::native::arm_feature::neon_bf16))
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#else
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#define NATIVE_DETAIL_MIN_NEON_BF16 (::native::isa<>{})
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#endif
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#ifdef __AVXIFMA__
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#define NATIVE_DETAIL_MIN_AVXIFMA (::native::isa<>(::native::x86_feature::avxifma))
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#else
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#define NATIVE_DETAIL_MIN_AVXIFMA (::native::isa<>{})
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#endif
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#ifdef __SHA512__
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#define NATIVE_DETAIL_MIN_X86_SHA512 (::native::isa<>(::native::x86_feature::sha512))
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#else
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#define NATIVE_DETAIL_MIN_X86_SHA512 (::native::isa<>{})
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#endif
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#ifdef __SM3__
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#define NATIVE_DETAIL_MIN_X86_SM3 (::native::isa<>(::native::x86_feature::sm3))
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#else
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#define NATIVE_DETAIL_MIN_X86_SM3 (::native::isa<>{})
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#endif
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#ifdef __SM4__
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#define NATIVE_DETAIL_MIN_X86_SM4 (::native::isa<>(::native::x86_feature::sm4))
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#else
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#define NATIVE_DETAIL_MIN_X86_SM4 (::native::isa<>{})
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#endif
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#ifdef __AVXNECONVERT__
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#define NATIVE_DETAIL_MIN_X86_AVXNECONVERT (::native::isa<>(::native::x86_feature::avxneconvert))
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#else
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#define NATIVE_DETAIL_MIN_X86_AVXNECONVERT (::native::isa<>{})
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#endif
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#ifdef __ADX__
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#define NATIVE_DETAIL_MIN_ADX (::native::isa<>(::native::x86_feature::adx))
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#else
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#define NATIVE_DETAIL_MIN_ADX (::native::isa<>{})
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#endif
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#ifdef __SHA__
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#define NATIVE_DETAIL_MIN_SHA (::native::isa<>(::native::x86_feature::sha))
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#else
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#define NATIVE_DETAIL_MIN_SHA (::native::isa<>{})
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#endif
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#ifdef __VAES__
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#define NATIVE_DETAIL_MIN_VAES (::native::isa<>(::native::x86_feature::vaes))
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#else
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#define NATIVE_DETAIL_MIN_VAES (::native::isa<>{})
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#endif
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#ifdef __AES__
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#define NATIVE_DETAIL_MIN_AES (::native::isa<>(::native::x86_feature::aes))
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#else
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#define NATIVE_DETAIL_MIN_AES (::native::isa<>{})
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#endif
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#ifdef __VPCLMULQDQ__
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#define NATIVE_DETAIL_MIN_VPCLMULQDQ (::native::isa<>(::native::x86_feature::vpclmulqdq))
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#else
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#define NATIVE_DETAIL_MIN_VPCLMULQDQ (::native::isa<>{})
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#endif
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#ifdef __PCLMUL__
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#define NATIVE_DETAIL_MIN_PCLMUL (::native::isa<>(::native::x86_feature::pclmul))
332
#else
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#define NATIVE_DETAIL_MIN_PCLMUL (::native::isa<>{})
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#endif
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#if defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16) && (defined(__x86_64__) || defined(_M_X64))
336
#define NATIVE_DETAIL_MIN_CX16 (::native::isa<>(::native::x86_feature::cx16))
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#else
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#define NATIVE_DETAIL_MIN_CX16 (::native::isa<>{})
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#endif
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#ifdef __AVX512CD__
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#define NATIVE_DETAIL_MIN_AVX512CD (::native::isa<>(::native::x86_feature::avx512cd))
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#else
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#define NATIVE_DETAIL_MIN_AVX512CD (::native::isa<>{})
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#endif
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#ifdef __AVX512IFMA__
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#define NATIVE_DETAIL_MIN_AVX512IFMA (::native::isa<>(::native::x86_feature::avx512ifma))
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#else
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#define NATIVE_DETAIL_MIN_AVX512IFMA (::native::isa<>{})
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#endif
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#ifdef __LZCNT__
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#define NATIVE_DETAIL_MIN_LZCNT (::native::isa<>(::native::x86_feature::lzcnt))
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#else
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#define NATIVE_DETAIL_MIN_LZCNT (::native::isa<>{})
355
#endif
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#ifdef __MOVBE__
357
#define NATIVE_DETAIL_MIN_MOVBE (::native::isa<>(::native::x86_feature::movbe))
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#else
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#define NATIVE_DETAIL_MIN_MOVBE (::native::isa<>{})
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#endif
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#ifdef __LAHF_SAHF__
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#define NATIVE_DETAIL_MIN_SAHF (::native::isa<>(::native::x86_feature::sahf))
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#else
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#define NATIVE_DETAIL_MIN_SAHF (::native::isa<>{})
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#endif
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#ifdef __MWAITX__
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#define NATIVE_DETAIL_MIN_MWAITX (::native::isa<>(::native::x86_feature::mwaitx))
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#else
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#define NATIVE_DETAIL_MIN_MWAITX (::native::isa<>{})
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#endif
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#ifdef __WAITPKG__
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#define NATIVE_DETAIL_MIN_WAITPKG (::native::isa<>(::native::x86_feature::waitpkg))
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#else
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#define NATIVE_DETAIL_MIN_WAITPKG (::native::isa<>{})
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#endif
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#ifdef __CRC32__
377
#define NATIVE_DETAIL_MIN_CRC32 (::native::isa<>(::native::x86_feature::crc32))
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#else
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#define NATIVE_DETAIL_MIN_CRC32 (::native::isa<>{})
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#endif
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#ifdef __GFNI__
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#define NATIVE_DETAIL_MIN_GFNI (::native::isa<>(::native::x86_feature::gfni))
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#else
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#define NATIVE_DETAIL_MIN_GFNI (::native::isa<>{})
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#endif
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#ifdef __ARM_FEATURE_AES
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#define NATIVE_DETAIL_MIN_ARM_AES (::native::arm_feature::aes&::native::arm_feature::pmull)
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#else
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#define NATIVE_DETAIL_MIN_ARM_AES (::native::isa<>{})
390
#endif
391
#ifdef __ARM_FEATURE_SHA2
392
#define NATIVE_DETAIL_MIN_ARM_SHA2 (::native::arm_feature::sha1&::native::arm_feature::sha2)
393
#else
394
#define NATIVE_DETAIL_MIN_ARM_SHA2 (::native::isa<>{})
395
#endif
396
#ifdef __ARM_FEATURE_SHA3
397
#define NATIVE_DETAIL_MIN_ARM_SHA3 (::native::isa<>(::native::arm_feature::sha3))
398
#else
399
#define NATIVE_DETAIL_MIN_ARM_SHA3 (::native::isa<>{})
400
#endif
401
#ifdef __ARM_FEATURE_SHA512
402
#define NATIVE_DETAIL_MIN_ARM_SHA512 (::native::arm_feature::sha1&::native::arm_feature::sha2&::native::arm_feature::sha512)
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#else
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#define NATIVE_DETAIL_MIN_ARM_SHA512 (::native::isa<>{})
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#endif
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#ifdef __ARM_FEATURE_SM3
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#define NATIVE_DETAIL_MIN_ARM_SM3 (::native::isa<>(::native::arm_feature::sm3))
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#else
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#define NATIVE_DETAIL_MIN_ARM_SM3 (::native::isa<>{})
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#endif
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#ifdef __ARM_FEATURE_SM4
412
#define NATIVE_DETAIL_MIN_ARM_SM4 (::native::isa<>(::native::arm_feature::sm4))
413
#else
414
#define NATIVE_DETAIL_MIN_ARM_SM4 (::native::isa<>{})
415
#endif
416
#ifdef __ARM_FEATURE_CRC32
417
#define NATIVE_DETAIL_MIN_ARM_CRC (::native::isa<>(::native::arm_feature::crc))
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#else
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#define NATIVE_DETAIL_MIN_ARM_CRC (::native::isa<>{})
420
#endif
421
#ifdef __ARM_FEATURE_ATOMICS
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#define NATIVE_DETAIL_MIN_ARM_LSE (::native::isa<>(::native::arm_feature::lse))
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#else
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#define NATIVE_DETAIL_MIN_ARM_LSE (::native::isa<>{})
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#endif
426
#ifdef __ARM_FEATURE_QRDMX
427
#define NATIVE_DETAIL_MIN_ARM_RDM (::native::isa<>(::native::arm_feature::rdm))
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#else
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#define NATIVE_DETAIL_MIN_ARM_RDM (::native::isa<>{})
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#endif
431
#ifdef __ARM_FEATURE_FP16_FML
432
#define NATIVE_DETAIL_MIN_ARM_FP16FML (::native::isa<>(::native::arm_feature::fp16fml))
433
#else
434
#define NATIVE_DETAIL_MIN_ARM_FP16FML (::native::isa<>{})
435
#endif
436
#ifdef __ARM_FEATURE_DOTPROD
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#define NATIVE_DETAIL_MIN_ARM_DOTPROD (::native::isa<>(::native::arm_feature::dotprod))
438
#else
439
#define NATIVE_DETAIL_MIN_ARM_DOTPROD (::native::isa<>{})
440
#endif
441
#ifdef __ARM_FEATURE_COMPLEX
442
#define NATIVE_DETAIL_MIN_ARM_COMPLEX (::native::isa<>(::native::arm_feature::complxnum))
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#else
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#define NATIVE_DETAIL_MIN_ARM_COMPLEX (::native::isa<>{})
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#endif
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#ifdef __ARM_FEATURE_JCVT
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#define NATIVE_DETAIL_MIN_ARM_JSCVT (::native::isa<>(::native::arm_feature::jsconv))
448
#else
449
#define NATIVE_DETAIL_MIN_ARM_JSCVT (::native::isa<>{})
450
#endif
451
#ifdef __ARM_FEATURE_RCPC
452
#define NATIVE_DETAIL_MIN_ARM_RCPC (::native::isa<>(::native::arm_feature::rcpc))
453
#else
454
#define NATIVE_DETAIL_MIN_ARM_RCPC (::native::isa<>{})
455
#endif
456
#ifdef __ARM_FEATURE_MATMUL_INT8
457
#define NATIVE_DETAIL_MIN_ARM_I8MM (::native::isa<>(::native::arm_feature::i8mm))
458
#else
459
#define NATIVE_DETAIL_MIN_ARM_I8MM (::native::isa<>{})
460
#endif
461
#ifdef __ARM_FEATURE_PAUTH
462
#define NATIVE_DETAIL_MIN_ARM_PAUTH (::native::isa<>(::native::arm_feature::pauth))
463
#else
464
#define NATIVE_DETAIL_MIN_ARM_PAUTH (::native::isa<>{})
465
#endif
466
467
#ifdef __wasm_simd128__
468
#define NATIVE_DETAIL_MIN_WASM_SIMD128 (::native::isa<>(::native::wasm_feature::simd128))
469
#else
470
#define NATIVE_DETAIL_MIN_WASM_SIMD128 (::native::isa<>{})
471
#endif
472
#ifdef __wasm_relaxed_simd__
473
#define NATIVE_DETAIL_MIN_WASM_RELAXED_SIMD (::native::isa<>(::native::wasm_feature::relaxed_simd))
474
#else
475
#define NATIVE_DETAIL_MIN_WASM_RELAXED_SIMD (::native::isa<>{})
476
#endif
477
478
#if defined(__SSE4A__) || defined(__XOP__) || defined(__FMA4__) || \
479
defined(__AVX512VP2INTERSECT__) || \
480
defined(__AMX_TILE__) || defined(__AMX_INT8__) || defined(__AMX_BF16__) || \
481
defined(__ARM_FEATURE_SVE) || defined(__ARM_FEATURE_SME)
482
#define NATIVE_DETAIL_MIN_UNREGISTERED (::native::target_features("unregistered"))
483
#else
484
#define NATIVE_DETAIL_MIN_UNREGISTERED (::native::isa<>{})
485
#endif
486
487
// Optional additional project contract. This is an ISA value/expression (for
488
// example ::native::target_features("avx2,f16c")), never a CPU-name guess. The ordinary
489
// executable's minimum remains a startup precondition: the selector itself must
490
// already be safe to run. Compiler CPU models can enable features not represented
491
// by predefines; this macro is not an inference engine for arbitrary -mcpu flags.
492
#ifndef NATIVE_TARGET_EXTRA_MINIMUM
493
#define NATIVE_TARGET_EXTRA_MINIMUM (::native::isa<>{})
494
#endif
495
// The current translation unit's known enabled instruction features. Clang has
496
// already resolved command-line implications and explicit negative flags. Do not
497
// apply feature_closure here: it could re-enable a deliberately disabled feature.
498
// This textual expression belongs to the consumer, not a precompiled module.
499
// Function target attributes and target pragmas do not change this snapshot.
500
#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
501
#define NATIVE_DETAIL_BASELINE_NEON_FP16 (::native::isa<>(::native::arm_feature::neon_fp16))
502
#else
503
#define NATIVE_DETAIL_BASELINE_NEON_FP16 (::native::isa<>{})
504
#endif
505
// Some architecture-version macros survive -mgeneral-regs-only. SIMD
506
// operations are available only when the vector register target is enabled.
507
#define NATIVE_DETAIL_MIN_ARM_SIMD_EXTRAS (NATIVE_DETAIL_MIN_NEON_BF16& \
508
NATIVE_DETAIL_MIN_ARM_AES&NATIVE_DETAIL_MIN_ARM_SHA2&NATIVE_DETAIL_MIN_ARM_SHA3&NATIVE_DETAIL_MIN_ARM_SHA512& \
509
NATIVE_DETAIL_MIN_ARM_SM3&NATIVE_DETAIL_MIN_ARM_SM4& \
510
NATIVE_DETAIL_MIN_ARM_RDM&NATIVE_DETAIL_MIN_ARM_FP16FML&NATIVE_DETAIL_MIN_ARM_DOTPROD& \
511
NATIVE_DETAIL_MIN_ARM_COMPLEX&NATIVE_DETAIL_MIN_ARM_I8MM)
512
#ifdef __ARM_NEON
513
#define NATIVE_DETAIL_BASELINE_ARM_SIMD_EXTRAS NATIVE_DETAIL_MIN_ARM_SIMD_EXTRAS
514
#else
515
#define NATIVE_DETAIL_BASELINE_ARM_SIMD_EXTRAS (::native::isa<>{})
516
#endif
517
#if defined(__ARM_FP) && (__ARM_FP & 8)
518
#define NATIVE_DETAIL_BASELINE_ARM_JSCVT NATIVE_DETAIL_MIN_ARM_JSCVT
519
#else
520
#define NATIVE_DETAIL_BASELINE_ARM_JSCVT (::native::isa<>{})
521
#endif
522
#define NATIVE_BASELINE (\
523
NATIVE_DETAIL_MIN_MMX&NATIVE_DETAIL_MIN_SSE&NATIVE_DETAIL_MIN_SSE2&NATIVE_DETAIL_MIN_SSE3& \
524
NATIVE_DETAIL_MIN_SSSE3&NATIVE_DETAIL_MIN_SSE41&NATIVE_DETAIL_MIN_SSE42&NATIVE_DETAIL_MIN_POPCNT& \
525
NATIVE_DETAIL_MIN_AVX&NATIVE_DETAIL_MIN_AVX2&NATIVE_DETAIL_MIN_FMA&NATIVE_DETAIL_MIN_F16C& \
526
NATIVE_DETAIL_MIN_BMI1&NATIVE_DETAIL_MIN_BMI2&NATIVE_DETAIL_MIN_AVX512F&NATIVE_DETAIL_MIN_AVX512DQ& \
527
NATIVE_DETAIL_MIN_AVX512BW&NATIVE_DETAIL_MIN_AVX512VL&NATIVE_DETAIL_MIN_AVX512BF16&NATIVE_DETAIL_MIN_AVX512FP16& \
528
NATIVE_DETAIL_MIN_AVX512VBMI&NATIVE_DETAIL_MIN_AVX512VBMI2& \
529
NATIVE_DETAIL_MIN_AVX512BITALG&NATIVE_DETAIL_MIN_AVX512VPOPCNTDQ& \
530
NATIVE_DETAIL_MIN_AVXVNNI&NATIVE_DETAIL_MIN_AVX512VNNI&NATIVE_DETAIL_MIN_AVXVNNIINT8&NATIVE_DETAIL_MIN_AVXVNNIINT16& \
531
NATIVE_DETAIL_MIN_NEON&NATIVE_DETAIL_BASELINE_NEON_FP16&NATIVE_DETAIL_BASELINE_ARM_SIMD_EXTRAS& \
532
NATIVE_DETAIL_MIN_AES&NATIVE_DETAIL_MIN_SHA&NATIVE_DETAIL_MIN_VAES&NATIVE_DETAIL_MIN_AVXIFMA&NATIVE_DETAIL_MIN_ADX&NATIVE_DETAIL_MIN_X86_SHA512&NATIVE_DETAIL_MIN_X86_SM3&NATIVE_DETAIL_MIN_X86_SM4&NATIVE_DETAIL_MIN_X86_AVXNECONVERT&NATIVE_DETAIL_MIN_PCLMUL&NATIVE_DETAIL_MIN_VPCLMULQDQ&NATIVE_DETAIL_MIN_CX16&NATIVE_DETAIL_MIN_AVX512CD& \
533
NATIVE_DETAIL_MIN_AVX512IFMA&NATIVE_DETAIL_MIN_LZCNT&NATIVE_DETAIL_MIN_MOVBE&NATIVE_DETAIL_MIN_SAHF& \
534
NATIVE_DETAIL_MIN_MWAITX&NATIVE_DETAIL_MIN_WAITPKG&NATIVE_DETAIL_MIN_CRC32&NATIVE_DETAIL_MIN_GFNI& \
535
NATIVE_DETAIL_MIN_ARM_CRC&NATIVE_DETAIL_MIN_ARM_LSE&NATIVE_DETAIL_BASELINE_ARM_JSCVT& \
536
NATIVE_DETAIL_MIN_ARM_RCPC&NATIVE_DETAIL_MIN_ARM_PAUTH& \
537
NATIVE_DETAIL_MIN_WASM_SIMD128&NATIVE_DETAIL_MIN_WASM_RELAXED_SIMD)
538
539
// Source-variant admission retains its conservative inherited minimum and any
540
// additional deployment requirements, separately from the exact known baseline.
541
#define NATIVE_TARGET_MINIMUM (::native::feature_closure(NATIVE_TARGET_EXTRA_MINIMUM& \
542
NATIVE_BASELINE&NATIVE_DETAIL_MIN_NEON_FP16&NATIVE_DETAIL_MIN_ARM_SIMD_EXTRAS& \
543
NATIVE_DETAIL_MIN_ARM_JSCVT&NATIVE_DETAIL_MIN_UNREGISTERED))
544
545
// Admission follows the same order as the compile-time choice pack.
546
#define NATIVE_DETAIL_TARGET_LIST(unused,tag) \
547
+::native::isa_list<::native::target_entry{NATIVE_TARGET_ISA(tag),NATIVE_TARGET_MINIMUM}>{}
548
#define NATIVE_TARGET_LIST(...) \
549
(::native::isa_list<>{} NATIVE_DETAIL_TARGET_MAP(NATIVE_DETAIL_TARGET_LIST,unused,__VA_ARGS__))
src
native
targets.h
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