FHM

Collaboration diagram for FHM:

Functions
template<isa< arm > Arch> requires (Arch.has(arm_feature::fp16fml))
constexpr simd< float, 2, Arch >	native::fmlal (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Add products from the low 2 half lanes of a and b.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 4)
constexpr simd< float, 2, Arch >	native::fmlal_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FMLAL with b[Lane] broadcast; selects the low 2 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 8)
constexpr simd< float, 2, Arch >	native::fmlal_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FMLAL with b[Lane] broadcast; selects the low 2 lanes of a.
template<isa< arm > Arch> requires (Arch.has(arm_feature::fp16fml))
constexpr simd< float, 4, Arch >	native::fmlal (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Add products from the low 4 half lanes of a and b.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 4)
constexpr simd< float, 4, Arch >	native::fmlal_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FMLAL with b[Lane] broadcast; selects the low 4 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 8)
constexpr simd< float, 4, Arch >	native::fmlal_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FMLAL with b[Lane] broadcast; selects the low 4 lanes of a.
template<isa< arm > Arch> requires (Arch.has(arm_feature::fp16fml))
constexpr simd< float, 2, Arch >	native::fmlal2 (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Add products from the high 2 half lanes of a and b.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 4)
constexpr simd< float, 2, Arch >	native::fmlal2_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FMLAL2 with b[Lane] broadcast; selects the high 2 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 8)
constexpr simd< float, 2, Arch >	native::fmlal2_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FMLAL2 with b[Lane] broadcast; selects the high 2 lanes of a.
template<isa< arm > Arch> requires (Arch.has(arm_feature::fp16fml))
constexpr simd< float, 4, Arch >	native::fmlal2 (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Add products from the high 4 half lanes of a and b.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 4)
constexpr simd< float, 4, Arch >	native::fmlal2_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FMLAL2 with b[Lane] broadcast; selects the high 4 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 8)
constexpr simd< float, 4, Arch >	native::fmlal2_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FMLAL2 with b[Lane] broadcast; selects the high 4 lanes of a.
template<isa< arm > Arch> requires (Arch.has(arm_feature::fp16fml))
constexpr simd< float, 2, Arch >	native::fmlsl (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Subtract products from the low 2 half lanes of a and b.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 4)
constexpr simd< float, 2, Arch >	native::fmlsl_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FMLSL with b[Lane] broadcast; selects the low 2 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 8)
constexpr simd< float, 2, Arch >	native::fmlsl_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FMLSL with b[Lane] broadcast; selects the low 2 lanes of a.
template<isa< arm > Arch> requires (Arch.has(arm_feature::fp16fml))
constexpr simd< float, 4, Arch >	native::fmlsl (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Subtract products from the low 4 half lanes of a and b.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 4)
constexpr simd< float, 4, Arch >	native::fmlsl_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FMLSL with b[Lane] broadcast; selects the low 4 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 8)
constexpr simd< float, 4, Arch >	native::fmlsl_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FMLSL with b[Lane] broadcast; selects the low 4 lanes of a.
template<isa< arm > Arch> requires (Arch.has(arm_feature::fp16fml))
constexpr simd< float, 2, Arch >	native::fmlsl2 (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Subtract products from the high 2 half lanes of a and b.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 4)
constexpr simd< float, 2, Arch >	native::fmlsl2_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FMLSL2 with b[Lane] broadcast; selects the high 2 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 8)
constexpr simd< float, 2, Arch >	native::fmlsl2_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FMLSL2 with b[Lane] broadcast; selects the high 2 lanes of a.
template<isa< arm > Arch> requires (Arch.has(arm_feature::fp16fml))
constexpr simd< float, 4, Arch >	native::fmlsl2 (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Subtract products from the high 4 half lanes of a and b.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 4)
constexpr simd< float, 4, Arch >	native::fmlsl2_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FMLSL2 with b[Lane] broadcast; selects the high 4 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 8)
constexpr simd< float, 4, Arch >	native::fmlsl2_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FMLSL2 with b[Lane] broadcast; selects the high 4 lanes of a.

Detailed Description

Runtime calls require arm_feature::fp16fml (FEAT_FHM), independently of FCMA/BF16. Binary16 inputs accumulate directly into binary32, with one rounding. FPCR controls and FPSR effects are those of the instruction; neither is reset. Volatile assembly retains status effects even when the result is unused. Constant evaluation uses RNE, gradual inputs/results, DN=AH=AHP=FZ=FZ16=FIZ=EBF=0, with masked exceptions and no status effects; fixed instruction rules still apply. Missing-feature overloads are consteval-only and require complete storage types.