Architecture-tagged vectors, register packs and supporting value types. Native arithmetic follows its architecture tag and instruction-set preconditions. Common utilities do not select or admit a runtime CPU profile. More...

Classes
struct	abi_lookup
struct	arm_capabilities
class	basic_static_string
	A view of one complete interned string, with its length retained. The five standard character widths are supported by the _ss literal. Embedded NUL characters remain part of its length. Default construction selects the canonical empty string. The view constructor is a compatibility escape hatch, not a runtime interning operation: arbitrary string_view storage violates the lifetime and pointer-equality/hash contract. More...
struct	bf16
struct	c_free
struct	compaction_result
struct	cpuid_t
struct	fp16
struct	imm_t
struct	isa
	A structural set of one family's features, without prerequisite closure. More...
struct	isa< arm >
	Exact ARM feature requirements; construction does not add prerequisites. More...
struct	isa< wasm >
	Exact WebAssembly feature requirements; construction does not add prerequisites. More...
struct	isa< x86 >
	Exact X86 feature requirements; construction does not add prerequisites. More...
struct	isa_admission
	Admission result for requirements from one architecture family. More...
struct	mask_lane
struct	mask_traits
struct	mask_traits< bf16 >
struct	mask_traits< fp16 >
struct	mask_traits< mask_lane< U > >
struct	mask_traits< predicate< N, Arch > >
struct	mask_traits< simd< T, N, Arch > >
struct	mask_traits< std::array< T, N > >
struct	mask_traits< T >
struct	mwaitx
	waiter using the MONITORX/MWAITX instruction feature More...
struct	predicate
struct	predicate< N, A >
	Compact logical mask for register-only instruction shapes. More...
struct	predicate< N, Arch >
struct	reify
	Store a compile-time sequence followed by one value-initialized terminator. More...
struct	simd
	Omitted architecture arguments use the native.simd provider's baseline. More...
struct	simd< bf16, 8, Arch >
struct	simd< bf16, N, Arch >
struct	simd< bool, N, Arch >
struct	simd< float, 4, Arch >
struct	simd< float, 8, Arch >
struct	simd< fp16, 32, Arch >
struct	simd< fp16, 8, Arch >
struct	simd< mask_lane< U >, N, A >
	Canonical zero/all-one SIMD128 comparison lanes. More...
struct	simd< T, N, A >
	One complete WebAssembly SIMD128 register with semantic element lanes. More...
struct	simd< T, N, Arch >
struct	simd_customization
struct	simd_memory
struct	simd_traits
struct	spin
	A universally supported x86 spin waiter using PAUSE; monitor is a no-op. More...
class	static_c_string
	A pointer-sized view of a complete interned char string. Length is recovered from the first NUL. Use static_string when embedded NULs matter or repeated end/length scans are undesirable. Default construction selects the canonical empty string; equality compares addresses. More...
struct	target_entry
	A source variant retains its requested ISA and inherited compiler minimum. More...
struct	umwait
	waiter using the WAITPKG instruction feature More...
struct	wasm_capabilities
struct	wide
	Own N values of T, including an empty pack when N == 0. registers is the underlying array. Tuple access and structured bindings refer to the actual elements. Value initialization follows T's rules; no general floating-point or zero-initialization policy is added here. More...
struct	x86_capabilities

Concepts
concept	arch
	A feature enum or an ISA value from one architecture family.
concept	not_one_of
	`N` is not one of the `candidates`
concept	not_one_of_t
	type `T` is not one of the `candidates`
concept	one_of
	`N` is one of the `candidates`
concept	one_of_t
	type `T` is one of the `candidates`
concept	trivially_destructible
concept	waiter
	some way to wait for a value to change

Typedefs
template<trivially_destructible T>
using	unique_c_ptr = std::unique_ptr<T, c_free>
using	unique_str = unique_c_ptr<char const>
template<typename T>
using	int_t
template<typename T>
using	uint_t
template<class T>
using	mask = typename mask_traits<std::remove_cvref_t<T>>::type
template<class T>
using	mask
	Export mask lookup after removing the value type's cv/ref qualifiers.

Enumerations
enum class	CMPINT : std::size_t { CMPINT::EQ = 0x0uz , CMPINT::LT = 0x1uz , CMPINT::LE = 0x2uz , CMPINT::FALSE = 0x3uz , CMPINT::NE = 0x4uz , CMPINT::NLT = 0x5uz , CMPINT::NLE = 0x6uz , CMPINT::TRUE = 0x7uz }
	Scalar integer-comparison predicates, encoded like the corresponding x86 immediates. More...
enum class	CMP : std::size_t { CMP::EQ_OQ = 0x00uz , CMP::LT_OS = 0x01uz , CMP::LE_OS = 0x02uz , CMP::UNORD_Q = 0x03uz , CMP::NEQ_UQ = 0x04uz , CMP::NLT_US = 0x05uz , CMP::NLE_US = 0x06uz , CMP::ORD_Q = 0x07uz , CMP::EQ_UQ = 0x08uz , CMP::NGE_US = 0x09uz , CMP::NGT_US = 0x0Auz , CMP::FALSE_OQ = 0x0Buz , CMP::NEQ_OQ = 0x0Cuz , CMP::GE_OS = 0x0Duz , CMP::GT_OS = 0x0Euz , CMP::TRUE_UQ = 0x0Fuz , CMP::EQ_OS = 0x10uz , CMP::LT_OQ = 0x11uz , CMP::LE_OQ = 0x12uz , CMP::UNORD_S = 0x13uz , CMP::NEQ_US = 0x14uz , CMP::NLT_UQ = 0x15uz , CMP::NLE_UQ = 0x16uz , CMP::ORD_S = 0x17uz , CMP::EQ_US = 0x18uz , CMP::NGE_UQ = 0x19uz , CMP::NGT_UQ = 0x1Auz , CMP::FALSE_OS = 0x1Buz , CMP::NEQ_OS = 0x1Cuz , CMP::GE_OQ = 0x1Duz , CMP::GT_OQ = 0x1Euz , CMP::TRUE_US = 0x1Fuz }
	Scalar floating-comparison predicates, including ordered and unordered truth tables. More...
enum class	cpu_vendor : std::uint8_t { intel = 0 , amd = 1 , unknown = 2 }
	Recognized CPUID vendor strings; vendor identity alone does not imply features. More...
enum class	architecture
	Instruction-set families; an ISA value belongs to exactly one family.
enum class	simd_access
enum class	x86_feature : std::uint64_t
	Architecture-specific instruction features, represented by local bit indices.
enum class	arm_feature : std::uint64_t
	Independently observable ARM instruction features, using local bit indices.
enum class	wasm_feature : std::uint64_t
	WebAssembly validation capabilities, using local bit indices.
enum class	architecture
	Instruction-set families; an ISA value belongs to exactly one family.
enum class	x86_feature
	Architecture-specific instruction features, represented by local bit indices.
enum class	arm_feature
	Independently observable ARM instruction features, using local bit indices.
enum class	wasm_feature
	WebAssembly validation capabilities, using local bit indices.
enum class	simd_access
enum class	simd_access

Functions
template<isa< arm > Arch> requires (Arch.has(arm_feature::aes))
constexpr simd< std::uint8_t, 16, Arch >	aese (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > round_key) noexcept
	Apply AddRoundKey, SubBytes and ShiftRows to one AES state.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::aes) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	aese (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > round_key) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::aes))
constexpr simd< std::uint8_t, 16, Arch >	aesd (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > round_key) noexcept
	Apply AddRoundKey, inverse ShiftRows and inverse SubBytes to one AES state.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::aes) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	aesd (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > round_key) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::aes))
constexpr simd< std::uint8_t, 16, Arch >	aesmc (simd< std::uint8_t, 16, Arch > state) noexcept
	Apply AES MixColumns independently to the four state columns.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::aes) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	aesmc (simd< std::uint8_t, 16, Arch > state) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::aes))
constexpr simd< std::uint8_t, 16, Arch >	aesimc (simd< std::uint8_t, 16, Arch > state) noexcept
	Apply inverse AES MixColumns independently to the four state columns.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::aes) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	aesimc (simd< std::uint8_t, 16, Arch > state) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, class... T>
void	aese (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	aesd (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	aesmc (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	aesimc (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch> requires (Arch.has(arm_feature::neon_bf16))
constexpr simd< float, 2, Arch >	bfdot (simd< float, 2, Arch > acc, simd< bf16, 4, Arch > a, simd< bf16, 4, Arch > b) noexcept
	Accumulate each adjacent pair of BF16 products into the corresponding FP32 lane.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<bf16, 4, Arch>); } && !(Arch.has(arm_feature::neon_bf16)))
consteval simd< float, 2, Arch >	bfdot (simd< float, 2, Arch > acc, simd< bf16, 4, Arch > a, simd< bf16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::neon_bf16) && Lane < 2)
constexpr simd< float, 2, Arch >	bfdot_lane (simd< float, 2, Arch > acc, simd< bf16, 4, Arch > a, simd< bf16, 4, Arch > b) noexcept
	BFDOT with the BF16 pair b[2Lane], b[2Lane+1] shared by all output lanes.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<bf16, 4, Arch>); } && !(Arch.has(arm_feature::neon_bf16)) && Lane < 2)
consteval simd< float, 2, Arch >	bfdot_lane (simd< float, 2, Arch > acc, simd< bf16, 4, Arch > a, simd< bf16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::neon_bf16) && Lane < 4)
constexpr simd< float, 2, Arch >	bfdot_lane (simd< float, 2, Arch > acc, simd< bf16, 4, Arch > a, simd< bf16, 8, Arch > b) noexcept
	BFDOT with the BF16 pair b[2Lane], b[2Lane+1] shared by all output lanes.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<bf16, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && !(Arch.has(arm_feature::neon_bf16)) && Lane < 4)
consteval simd< float, 2, Arch >	bfdot_lane (simd< float, 2, Arch > acc, simd< bf16, 4, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch> requires (Arch.has(arm_feature::neon_bf16))
constexpr simd< float, 4, Arch >	bfdot (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Accumulate each adjacent pair of BF16 products into the corresponding FP32 lane.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && !(Arch.has(arm_feature::neon_bf16)))
consteval simd< float, 4, Arch >	bfdot (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::neon_bf16) && Lane < 2)
constexpr simd< float, 4, Arch >	bfdot_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 4, Arch > b) noexcept
	BFDOT with the BF16 pair b[2Lane], b[2Lane+1] shared by all output lanes.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && requires { sizeof(simd<bf16, 4, Arch>); } && !(Arch.has(arm_feature::neon_bf16)) && Lane < 2)
consteval simd< float, 4, Arch >	bfdot_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::neon_bf16) && Lane < 4)
constexpr simd< float, 4, Arch >	bfdot_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	BFDOT with the BF16 pair b[2Lane], b[2Lane+1] shared by all output lanes.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && !(Arch.has(arm_feature::neon_bf16)) && Lane < 4)
consteval simd< float, 4, Arch >	bfdot_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch> requires (Arch.has(arm_feature::neon_bf16))
constexpr simd< float, 4, Arch >	bfmmla (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Accumulate a row-major 2x4 matrix times a column-major 4x2 matrix, two BFDOT steps per result.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && !(Arch.has(arm_feature::neon_bf16)))
consteval simd< float, 4, Arch >	bfmmla (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch> requires (Arch.has(arm_feature::neon_bf16))
constexpr simd< float, 4, Arch >	bfmlalb (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Fused multiply-add of the even BF16 lanes into the corresponding FP32 lanes.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && !(Arch.has(arm_feature::neon_bf16)))
consteval simd< float, 4, Arch >	bfmlalb (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::neon_bf16) && Lane < 4)
constexpr simd< float, 4, Arch >	bfmlalb_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 4, Arch > b) noexcept
	Fused multiply-add of the even lanes of a with b[Lane] shared by all output lanes.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && requires { sizeof(simd<bf16, 4, Arch>); } && !(Arch.has(arm_feature::neon_bf16)) && Lane < 4)
consteval simd< float, 4, Arch >	bfmlalb_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::neon_bf16) && Lane < 8)
constexpr simd< float, 4, Arch >	bfmlalb_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Fused multiply-add of the even lanes of a with b[Lane] shared by all output lanes.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && !(Arch.has(arm_feature::neon_bf16)) && Lane < 8)
consteval simd< float, 4, Arch >	bfmlalb_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch> requires (Arch.has(arm_feature::neon_bf16))
constexpr simd< float, 4, Arch >	bfmlalt (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Fused multiply-add of the odd BF16 lanes into the corresponding FP32 lanes.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && !(Arch.has(arm_feature::neon_bf16)))
consteval simd< float, 4, Arch >	bfmlalt (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::neon_bf16) && Lane < 4)
constexpr simd< float, 4, Arch >	bfmlalt_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 4, Arch > b) noexcept
	Fused multiply-add of the odd lanes of a with b[Lane] shared by all output lanes.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && requires { sizeof(simd<bf16, 4, Arch>); } && !(Arch.has(arm_feature::neon_bf16)) && Lane < 4)
consteval simd< float, 4, Arch >	bfmlalt_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::neon_bf16) && Lane < 8)
constexpr simd< float, 4, Arch >	bfmlalt_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Fused multiply-add of the odd lanes of a with b[Lane] shared by all output lanes.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && !(Arch.has(arm_feature::neon_bf16)) && Lane < 8)
consteval simd< float, 4, Arch >	bfmlalt_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch> requires (Arch.has(arm_feature::dotprod))
constexpr simd< std::int32_t, 2, Arch >	sdot (simd< std::int32_t, 2, Arch > accumulator, simd< std::int8_t, 8, Arch > lhs, simd< std::int8_t, 8, Arch > rhs) noexcept
	SDOT: four byte products per accumulator lane, modulo 2^32.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::dotprod) && requires { sizeof(simd<std::int32_t, 2, Arch>); sizeof(simd<std::int8_t, 8, Arch>); })
consteval simd< std::int32_t, 2, Arch >	sdot (simd< std::int32_t, 2, Arch > accumulator, simd< std::int8_t, 8, Arch > lhs, simd< std::int8_t, 8, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::dotprod) && Lane >= 0 && Lane < 2)
constexpr simd< std::int32_t, 2, Arch >	sdot_lane (simd< std::int32_t, 2, Arch > accumulator, simd< std::int8_t, 8, Arch > lhs, simd< std::int8_t, 8, Arch > rhs) noexcept
	SDOT by element: broadcast rhs byte group Lane to every accumulator lane.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::dotprod) && Lane >= 0 && Lane < 2 && requires { sizeof(simd<std::int32_t, 2, Arch>); sizeof(simd <std::int8_t, 8, Arch>); })
consteval simd< std::int32_t, 2, Arch >	sdot_lane (simd< std::int32_t, 2, Arch > accumulator, simd< std::int8_t, 8, Arch > lhs, simd< std::int8_t, 8, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::dotprod) && Lane >= 0 && Lane < 4)
constexpr simd< std::int32_t, 2, Arch >	sdot_lane (simd< std::int32_t, 2, Arch > accumulator, simd< std::int8_t, 8, Arch > lhs, simd< std::int8_t, 16, Arch > rhs) noexcept
	SDOT by element: broadcast rhs byte group Lane to every accumulator lane.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::dotprod) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::int32_t, 2, Arch>); sizeof(simd <std::int8_t, 8, Arch>); sizeof(simd<std::int8_t, 16, Arch>); })
consteval simd< std::int32_t, 2, Arch >	sdot_lane (simd< std::int32_t, 2, Arch > accumulator, simd< std::int8_t, 8, Arch > lhs, simd< std::int8_t, 16, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::dotprod))
constexpr simd< std::int32_t, 4, Arch >	sdot (simd< std::int32_t, 4, Arch > accumulator, simd< std::int8_t, 16, Arch > lhs, simd< std::int8_t, 16, Arch > rhs) noexcept
	SDOT: four byte products per accumulator lane, modulo 2^32.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::dotprod) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int8_t, 16, Arch>); })
consteval simd< std::int32_t, 4, Arch >	sdot (simd< std::int32_t, 4, Arch > accumulator, simd< std::int8_t, 16, Arch > lhs, simd< std::int8_t, 16, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::dotprod) && Lane >= 0 && Lane < 2)
constexpr simd< std::int32_t, 4, Arch >	sdot_lane (simd< std::int32_t, 4, Arch > accumulator, simd< std::int8_t, 16, Arch > lhs, simd< std::int8_t, 8, Arch > rhs) noexcept
	SDOT by element: broadcast rhs byte group Lane to every accumulator lane.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::dotprod) && Lane >= 0 && Lane < 2 && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd <std::int8_t, 16, Arch>); sizeof(simd<std::int8_t, 8, Arch>); })
consteval simd< std::int32_t, 4, Arch >	sdot_lane (simd< std::int32_t, 4, Arch > accumulator, simd< std::int8_t, 16, Arch > lhs, simd< std::int8_t, 8, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::dotprod) && Lane >= 0 && Lane < 4)
constexpr simd< std::int32_t, 4, Arch >	sdot_lane (simd< std::int32_t, 4, Arch > accumulator, simd< std::int8_t, 16, Arch > lhs, simd< std::int8_t, 16, Arch > rhs) noexcept
	SDOT by element: broadcast rhs byte group Lane to every accumulator lane.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::dotprod) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd <std::int8_t, 16, Arch>); })
consteval simd< std::int32_t, 4, Arch >	sdot_lane (simd< std::int32_t, 4, Arch > accumulator, simd< std::int8_t, 16, Arch > lhs, simd< std::int8_t, 16, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::dotprod))
constexpr simd< std::uint32_t, 2, Arch >	udot (simd< std::uint32_t, 2, Arch > accumulator, simd< std::uint8_t, 8, Arch > lhs, simd< std::uint8_t, 8, Arch > rhs) noexcept
	UDOT: four byte products per accumulator lane, modulo 2^32.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::dotprod) && requires { sizeof(simd<std::uint32_t, 2, Arch>); sizeof(simd<std::uint8_t, 8, Arch>); })
consteval simd< std::uint32_t, 2, Arch >	udot (simd< std::uint32_t, 2, Arch > accumulator, simd< std::uint8_t, 8, Arch > lhs, simd< std::uint8_t, 8, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::dotprod) && Lane >= 0 && Lane < 2)
constexpr simd< std::uint32_t, 2, Arch >	udot_lane (simd< std::uint32_t, 2, Arch > accumulator, simd< std::uint8_t, 8, Arch > lhs, simd< std::uint8_t, 8, Arch > rhs) noexcept
	UDOT by element: broadcast rhs byte group Lane to every accumulator lane.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::dotprod) && Lane >= 0 && Lane < 2 && requires { sizeof(simd<std::uint32_t, 2, Arch>); sizeof(simd <std::uint8_t, 8, Arch>); })
consteval simd< std::uint32_t, 2, Arch >	udot_lane (simd< std::uint32_t, 2, Arch > accumulator, simd< std::uint8_t, 8, Arch > lhs, simd< std::uint8_t, 8, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::dotprod) && Lane >= 0 && Lane < 4)
constexpr simd< std::uint32_t, 2, Arch >	udot_lane (simd< std::uint32_t, 2, Arch > accumulator, simd< std::uint8_t, 8, Arch > lhs, simd< std::uint8_t, 16, Arch > rhs) noexcept
	UDOT by element: broadcast rhs byte group Lane to every accumulator lane.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::dotprod) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::uint32_t, 2, Arch>); sizeof(simd <std::uint8_t, 8, Arch>); sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint32_t, 2, Arch >	udot_lane (simd< std::uint32_t, 2, Arch > accumulator, simd< std::uint8_t, 8, Arch > lhs, simd< std::uint8_t, 16, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::dotprod))
constexpr simd< std::uint32_t, 4, Arch >	udot (simd< std::uint32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > lhs, simd< std::uint8_t, 16, Arch > rhs) noexcept
	UDOT: four byte products per accumulator lane, modulo 2^32.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::dotprod) && requires { sizeof(simd<std::uint32_t, 4, Arch>); sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	udot (simd< std::uint32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > lhs, simd< std::uint8_t, 16, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::dotprod) && Lane >= 0 && Lane < 2)
constexpr simd< std::uint32_t, 4, Arch >	udot_lane (simd< std::uint32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > lhs, simd< std::uint8_t, 8, Arch > rhs) noexcept
	UDOT by element: broadcast rhs byte group Lane to every accumulator lane.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::dotprod) && Lane >= 0 && Lane < 2 && requires { sizeof(simd<std::uint32_t, 4, Arch>); sizeof(simd <std::uint8_t, 16, Arch>); sizeof(simd<std::uint8_t, 8, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	udot_lane (simd< std::uint32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > lhs, simd< std::uint8_t, 8, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::dotprod) && Lane >= 0 && Lane < 4)
constexpr simd< std::uint32_t, 4, Arch >	udot_lane (simd< std::uint32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > lhs, simd< std::uint8_t, 16, Arch > rhs) noexcept
	UDOT by element: broadcast rhs byte group Lane to every accumulator lane.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::dotprod) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::uint32_t, 4, Arch>); sizeof(simd <std::uint8_t, 16, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	udot_lane (simd< std::uint32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > lhs, simd< std::uint8_t, 16, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, unsigned Rotation> requires (Arch.has(arm_feature::complxnum) && (Rotation == 90 \|\| Rotation == 270))
constexpr simd< float, 2, Arch >	fcadd (simd< float, 2, Arch > a, simd< float, 2, Arch > b) noexcept
	FCADD on 1 binary32 complex pair(s), rotation in degrees.
template<isa< arm > Arch, unsigned Rotation> requires (requires { sizeof(simd<float, 2, Arch>); } && !(Arch.has(arm_feature::complxnum)) && (Rotation == 90 \|\| Rotation == 270))
consteval simd< float, 2, Arch >	fcadd (simd< float, 2, Arch > a, simd< float, 2, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Rotation> requires (Arch.has(arm_feature::complxnum) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270))
constexpr simd< float, 2, Arch >	fcmla (simd< float, 2, Arch > acc, simd< float, 2, Arch > a, simd< float, 2, Arch > b) noexcept
	FCMLA on 1 binary32 complex pair(s), rotation in degrees.
template<isa< arm > Arch, unsigned Rotation> requires (requires { sizeof(simd<float, 2, Arch>); } && !(Arch.has(arm_feature::complxnum)) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270))
consteval simd< float, 2, Arch >	fcmla (simd< float, 2, Arch > acc, simd< float, 2, Arch > a, simd< float, 2, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Rotation, unsigned Lane> requires (Arch.has(arm_feature::complxnum) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270) && Lane < 1)
constexpr simd< float, 2, Arch >	fcmla_lane (simd< float, 2, Arch > acc, simd< float, 2, Arch > a, simd< float, 2, Arch > b) noexcept
	FCMLA using complex pair Lane of b (the lane indexes pairs, not scalars).
template<isa< arm > Arch, unsigned Rotation, unsigned Lane> requires (requires { sizeof(simd<float, 2, Arch>); } && !(Arch.has(arm_feature::complxnum)) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270) && Lane < 1)
consteval simd< float, 2, Arch >	fcmla_lane (simd< float, 2, Arch > acc, simd< float, 2, Arch > a, simd< float, 2, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Rotation, unsigned Lane> requires (Arch.has(arm_feature::complxnum) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270) && Lane < 2)
constexpr simd< float, 2, Arch >	fcmla_lane (simd< float, 2, Arch > acc, simd< float, 2, Arch > a, simd< float, 4, Arch > b) noexcept
	FCMLA using complex pair Lane of b (the lane indexes pairs, not scalars).
template<isa< arm > Arch, unsigned Rotation, unsigned Lane> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<float, 4, Arch>); } && !(Arch.has(arm_feature::complxnum)) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270) && Lane < 2)
consteval simd< float, 2, Arch >	fcmla_lane (simd< float, 2, Arch > acc, simd< float, 2, Arch > a, simd< float, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Rotation> requires (Arch.has(arm_feature::complxnum) && (Rotation == 90 \|\| Rotation == 270))
constexpr simd< float, 4, Arch >	fcadd (simd< float, 4, Arch > a, simd< float, 4, Arch > b) noexcept
	FCADD on 2 binary32 complex pair(s), rotation in degrees.
template<isa< arm > Arch, unsigned Rotation> requires (requires { sizeof(simd<float, 4, Arch>); } && !(Arch.has(arm_feature::complxnum)) && (Rotation == 90 \|\| Rotation == 270))
consteval simd< float, 4, Arch >	fcadd (simd< float, 4, Arch > a, simd< float, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Rotation> requires (Arch.has(arm_feature::complxnum) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270))
constexpr simd< float, 4, Arch >	fcmla (simd< float, 4, Arch > acc, simd< float, 4, Arch > a, simd< float, 4, Arch > b) noexcept
	FCMLA on 2 binary32 complex pair(s), rotation in degrees.
template<isa< arm > Arch, unsigned Rotation> requires (requires { sizeof(simd<float, 4, Arch>); } && !(Arch.has(arm_feature::complxnum)) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270))
consteval simd< float, 4, Arch >	fcmla (simd< float, 4, Arch > acc, simd< float, 4, Arch > a, simd< float, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Rotation, unsigned Lane> requires (Arch.has(arm_feature::complxnum) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270) && Lane < 1)
constexpr simd< float, 4, Arch >	fcmla_lane (simd< float, 4, Arch > acc, simd< float, 4, Arch > a, simd< float, 2, Arch > b) noexcept
	FCMLA using complex pair Lane of b (the lane indexes pairs, not scalars).
template<isa< arm > Arch, unsigned Rotation, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<float, 2, Arch>); } && !(Arch.has(arm_feature::complxnum)) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270) && Lane < 1)
consteval simd< float, 4, Arch >	fcmla_lane (simd< float, 4, Arch > acc, simd< float, 4, Arch > a, simd< float, 2, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Rotation, unsigned Lane> requires (Arch.has(arm_feature::complxnum) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270) && Lane < 2)
constexpr simd< float, 4, Arch >	fcmla_lane (simd< float, 4, Arch > acc, simd< float, 4, Arch > a, simd< float, 4, Arch > b) noexcept
	FCMLA using complex pair Lane of b (the lane indexes pairs, not scalars).
template<isa< arm > Arch, unsigned Rotation, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && !(Arch.has(arm_feature::complxnum)) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270) && Lane < 2)
consteval simd< float, 4, Arch >	fcmla_lane (simd< float, 4, Arch > acc, simd< float, 4, Arch > a, simd< float, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Rotation> requires (Arch.has(arm_feature::complxnum) && (Rotation == 90 \|\| Rotation == 270))
constexpr simd< double, 2, Arch >	fcadd (simd< double, 2, Arch > a, simd< double, 2, Arch > b) noexcept
	FCADD on 1 binary64 complex pair(s), rotation in degrees.
template<isa< arm > Arch, unsigned Rotation> requires (requires { sizeof(simd<double, 2, Arch>); } && !(Arch.has(arm_feature::complxnum)) && (Rotation == 90 \|\| Rotation == 270))
consteval simd< double, 2, Arch >	fcadd (simd< double, 2, Arch > a, simd< double, 2, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Rotation> requires (Arch.has(arm_feature::complxnum) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270))
constexpr simd< double, 2, Arch >	fcmla (simd< double, 2, Arch > acc, simd< double, 2, Arch > a, simd< double, 2, Arch > b) noexcept
	FCMLA on 1 binary64 complex pair(s), rotation in degrees.
template<isa< arm > Arch, unsigned Rotation> requires (requires { sizeof(simd<double, 2, Arch>); } && !(Arch.has(arm_feature::complxnum)) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270))
consteval simd< double, 2, Arch >	fcmla (simd< double, 2, Arch > acc, simd< double, 2, Arch > a, simd< double, 2, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Rotation> requires (Arch.has(arm_feature::complxnum) && Arch.has(arm_feature::neon_fp16) && (Rotation == 90 \|\| Rotation == 270))
constexpr simd< fp16, 4, Arch >	fcadd (simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FCADD on 2 binary16 complex pair(s), rotation in degrees.
template<isa< arm > Arch, unsigned Rotation> requires (requires { sizeof(simd<fp16, 4, Arch>); } && !(Arch.has(arm_feature::complxnum) && Arch.has(arm_feature::neon_fp16)) && (Rotation == 90 \|\| Rotation == 270))
consteval simd< fp16, 4, Arch >	fcadd (simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Rotation> requires (Arch.has(arm_feature::complxnum) && Arch.has(arm_feature::neon_fp16) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270))
constexpr simd< fp16, 4, Arch >	fcmla (simd< fp16, 4, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FCMLA on 2 binary16 complex pair(s), rotation in degrees.
template<isa< arm > Arch, unsigned Rotation> requires (requires { sizeof(simd<fp16, 4, Arch>); } && !(Arch.has(arm_feature::complxnum) && Arch.has(arm_feature::neon_fp16)) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270))
consteval simd< fp16, 4, Arch >	fcmla (simd< fp16, 4, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Rotation, unsigned Lane> requires (Arch.has(arm_feature::complxnum) && Arch.has(arm_feature::neon_fp16) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270) && Lane < 2)
constexpr simd< fp16, 4, Arch >	fcmla_lane (simd< fp16, 4, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FCMLA using complex pair Lane of b (the lane indexes pairs, not scalars).
template<isa< arm > Arch, unsigned Rotation, unsigned Lane> requires (requires { sizeof(simd<fp16, 4, Arch>); } && !(Arch.has(arm_feature::complxnum) && Arch.has(arm_feature::neon_fp16)) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270) && Lane < 2)
consteval simd< fp16, 4, Arch >	fcmla_lane (simd< fp16, 4, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Rotation, unsigned Lane> requires (Arch.has(arm_feature::complxnum) && Arch.has(arm_feature::neon_fp16) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270) && Lane < 4)
constexpr simd< fp16, 4, Arch >	fcmla_lane (simd< fp16, 4, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FCMLA using complex pair Lane of b (the lane indexes pairs, not scalars).
template<isa< arm > Arch, unsigned Rotation, unsigned Lane> requires (requires { sizeof(simd<fp16, 4, Arch>); } && requires { sizeof(simd<fp16, 8, Arch>); } && !(Arch.has(arm_feature::complxnum) && Arch.has(arm_feature::neon_fp16)) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270) && Lane < 4)
consteval simd< fp16, 4, Arch >	fcmla_lane (simd< fp16, 4, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Rotation> requires (Arch.has(arm_feature::complxnum) && Arch.has(arm_feature::neon_fp16) && (Rotation == 90 \|\| Rotation == 270))
constexpr simd< fp16, 8, Arch >	fcadd (simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FCADD on 4 binary16 complex pair(s), rotation in degrees.
template<isa< arm > Arch, unsigned Rotation> requires (requires { sizeof(simd<fp16, 8, Arch>); } && !(Arch.has(arm_feature::complxnum) && Arch.has(arm_feature::neon_fp16)) && (Rotation == 90 \|\| Rotation == 270))
consteval simd< fp16, 8, Arch >	fcadd (simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Rotation> requires (Arch.has(arm_feature::complxnum) && Arch.has(arm_feature::neon_fp16) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270))
constexpr simd< fp16, 8, Arch >	fcmla (simd< fp16, 8, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FCMLA on 4 binary16 complex pair(s), rotation in degrees.
template<isa< arm > Arch, unsigned Rotation> requires (requires { sizeof(simd<fp16, 8, Arch>); } && !(Arch.has(arm_feature::complxnum) && Arch.has(arm_feature::neon_fp16)) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270))
consteval simd< fp16, 8, Arch >	fcmla (simd< fp16, 8, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Rotation, unsigned Lane> requires (Arch.has(arm_feature::complxnum) && Arch.has(arm_feature::neon_fp16) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270) && Lane < 2)
constexpr simd< fp16, 8, Arch >	fcmla_lane (simd< fp16, 8, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FCMLA using complex pair Lane of b (the lane indexes pairs, not scalars).
template<isa< arm > Arch, unsigned Rotation, unsigned Lane> requires (requires { sizeof(simd<fp16, 8, Arch>); } && requires { sizeof(simd<fp16, 4, Arch>); } && !(Arch.has(arm_feature::complxnum) && Arch.has(arm_feature::neon_fp16)) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270) && Lane < 2)
consteval simd< fp16, 8, Arch >	fcmla_lane (simd< fp16, 8, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Rotation, unsigned Lane> requires (Arch.has(arm_feature::complxnum) && Arch.has(arm_feature::neon_fp16) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270) && Lane < 4)
constexpr simd< fp16, 8, Arch >	fcmla_lane (simd< fp16, 8, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FCMLA using complex pair Lane of b (the lane indexes pairs, not scalars).
template<isa< arm > Arch, unsigned Rotation, unsigned Lane> requires (requires { sizeof(simd<fp16, 8, Arch>); } && !(Arch.has(arm_feature::complxnum) && Arch.has(arm_feature::neon_fp16)) && (Rotation == 0 \|\| Rotation == 90 \|\| Rotation == 180 \|\| Rotation == 270) && Lane < 4)
consteval simd< fp16, 8, Arch >	fcmla_lane (simd< fp16, 8, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
arm_capabilities	observe_arm_capabilities () noexcept
template<isa< arm > Arch> requires (Arch.has(arm_feature::fp16fml))
constexpr simd< float, 2, Arch >	fmlal (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Add products from the low 2 half lanes of a and b.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<fp16, 4, Arch>); } && !(Arch.has(arm_feature::fp16fml)))
consteval simd< float, 2, Arch >	fmlal (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 4)
constexpr simd< float, 2, Arch >	fmlal_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FMLAL with b[Lane] broadcast; selects the low 2 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<fp16, 4, Arch>); } && !(Arch.has(arm_feature::fp16fml)) && Lane < 4)
consteval simd< float, 2, Arch >	fmlal_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 8)
constexpr simd< float, 2, Arch >	fmlal_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FMLAL with b[Lane] broadcast; selects the low 2 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<fp16, 4, Arch>); } && requires { sizeof(simd<fp16, 8, Arch>); } && !(Arch.has(arm_feature::fp16fml)) && Lane < 8)
consteval simd< float, 2, Arch >	fmlal_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch> requires (Arch.has(arm_feature::fp16fml))
constexpr simd< float, 4, Arch >	fmlal (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Add products from the low 4 half lanes of a and b.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<fp16, 8, Arch>); } && !(Arch.has(arm_feature::fp16fml)))
consteval simd< float, 4, Arch >	fmlal (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 4)
constexpr simd< float, 4, Arch >	fmlal_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FMLAL with b[Lane] broadcast; selects the low 4 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<fp16, 8, Arch>); } && requires { sizeof(simd<fp16, 4, Arch>); } && !(Arch.has(arm_feature::fp16fml)) && Lane < 4)
consteval simd< float, 4, Arch >	fmlal_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 8)
constexpr simd< float, 4, Arch >	fmlal_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FMLAL with b[Lane] broadcast; selects the low 4 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<fp16, 8, Arch>); } && !(Arch.has(arm_feature::fp16fml)) && Lane < 8)
consteval simd< float, 4, Arch >	fmlal_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch> requires (Arch.has(arm_feature::fp16fml))
constexpr simd< float, 2, Arch >	fmlal2 (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Add products from the high 2 half lanes of a and b.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<fp16, 4, Arch>); } && !(Arch.has(arm_feature::fp16fml)))
consteval simd< float, 2, Arch >	fmlal2 (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 4)
constexpr simd< float, 2, Arch >	fmlal2_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FMLAL2 with b[Lane] broadcast; selects the high 2 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<fp16, 4, Arch>); } && !(Arch.has(arm_feature::fp16fml)) && Lane < 4)
consteval simd< float, 2, Arch >	fmlal2_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 8)
constexpr simd< float, 2, Arch >	fmlal2_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FMLAL2 with b[Lane] broadcast; selects the high 2 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<fp16, 4, Arch>); } && requires { sizeof(simd<fp16, 8, Arch>); } && !(Arch.has(arm_feature::fp16fml)) && Lane < 8)
consteval simd< float, 2, Arch >	fmlal2_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch> requires (Arch.has(arm_feature::fp16fml))
constexpr simd< float, 4, Arch >	fmlal2 (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Add products from the high 4 half lanes of a and b.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<fp16, 8, Arch>); } && !(Arch.has(arm_feature::fp16fml)))
consteval simd< float, 4, Arch >	fmlal2 (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 4)
constexpr simd< float, 4, Arch >	fmlal2_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FMLAL2 with b[Lane] broadcast; selects the high 4 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<fp16, 8, Arch>); } && requires { sizeof(simd<fp16, 4, Arch>); } && !(Arch.has(arm_feature::fp16fml)) && Lane < 4)
consteval simd< float, 4, Arch >	fmlal2_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 8)
constexpr simd< float, 4, Arch >	fmlal2_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FMLAL2 with b[Lane] broadcast; selects the high 4 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<fp16, 8, Arch>); } && !(Arch.has(arm_feature::fp16fml)) && Lane < 8)
consteval simd< float, 4, Arch >	fmlal2_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch> requires (Arch.has(arm_feature::fp16fml))
constexpr simd< float, 2, Arch >	fmlsl (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Subtract products from the low 2 half lanes of a and b.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<fp16, 4, Arch>); } && !(Arch.has(arm_feature::fp16fml)))
consteval simd< float, 2, Arch >	fmlsl (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 4)
constexpr simd< float, 2, Arch >	fmlsl_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FMLSL with b[Lane] broadcast; selects the low 2 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<fp16, 4, Arch>); } && !(Arch.has(arm_feature::fp16fml)) && Lane < 4)
consteval simd< float, 2, Arch >	fmlsl_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 8)
constexpr simd< float, 2, Arch >	fmlsl_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FMLSL with b[Lane] broadcast; selects the low 2 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<fp16, 4, Arch>); } && requires { sizeof(simd<fp16, 8, Arch>); } && !(Arch.has(arm_feature::fp16fml)) && Lane < 8)
consteval simd< float, 2, Arch >	fmlsl_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch> requires (Arch.has(arm_feature::fp16fml))
constexpr simd< float, 4, Arch >	fmlsl (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Subtract products from the low 4 half lanes of a and b.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<fp16, 8, Arch>); } && !(Arch.has(arm_feature::fp16fml)))
consteval simd< float, 4, Arch >	fmlsl (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 4)
constexpr simd< float, 4, Arch >	fmlsl_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FMLSL with b[Lane] broadcast; selects the low 4 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<fp16, 8, Arch>); } && requires { sizeof(simd<fp16, 4, Arch>); } && !(Arch.has(arm_feature::fp16fml)) && Lane < 4)
consteval simd< float, 4, Arch >	fmlsl_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 8)
constexpr simd< float, 4, Arch >	fmlsl_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FMLSL with b[Lane] broadcast; selects the low 4 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<fp16, 8, Arch>); } && !(Arch.has(arm_feature::fp16fml)) && Lane < 8)
consteval simd< float, 4, Arch >	fmlsl_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch> requires (Arch.has(arm_feature::fp16fml))
constexpr simd< float, 2, Arch >	fmlsl2 (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Subtract products from the high 2 half lanes of a and b.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<fp16, 4, Arch>); } && !(Arch.has(arm_feature::fp16fml)))
consteval simd< float, 2, Arch >	fmlsl2 (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 4)
constexpr simd< float, 2, Arch >	fmlsl2_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FMLSL2 with b[Lane] broadcast; selects the high 2 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<fp16, 4, Arch>); } && !(Arch.has(arm_feature::fp16fml)) && Lane < 4)
consteval simd< float, 2, Arch >	fmlsl2_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 8)
constexpr simd< float, 2, Arch >	fmlsl2_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FMLSL2 with b[Lane] broadcast; selects the high 2 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<fp16, 4, Arch>); } && requires { sizeof(simd<fp16, 8, Arch>); } && !(Arch.has(arm_feature::fp16fml)) && Lane < 8)
consteval simd< float, 2, Arch >	fmlsl2_lane (simd< float, 2, Arch > acc, simd< fp16, 4, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch> requires (Arch.has(arm_feature::fp16fml))
constexpr simd< float, 4, Arch >	fmlsl2 (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Subtract products from the high 4 half lanes of a and b.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<fp16, 8, Arch>); } && !(Arch.has(arm_feature::fp16fml)))
consteval simd< float, 4, Arch >	fmlsl2 (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 4)
constexpr simd< float, 4, Arch >	fmlsl2_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 4, Arch > b) noexcept
	FMLSL2 with b[Lane] broadcast; selects the high 4 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<fp16, 8, Arch>); } && requires { sizeof(simd<fp16, 4, Arch>); } && !(Arch.has(arm_feature::fp16fml)) && Lane < 4)
consteval simd< float, 4, Arch >	fmlsl2_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::fp16fml) && Lane < 8)
constexpr simd< float, 4, Arch >	fmlsl2_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	FMLSL2 with b[Lane] broadcast; selects the high 4 lanes of a.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<fp16, 8, Arch>); } && !(Arch.has(arm_feature::fp16fml)) && Lane < 8)
consteval simd< float, 4, Arch >	fmlsl2_lane (simd< float, 4, Arch > acc, simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch> requires (Arch.has(arm_feature::i8mm))
constexpr simd< std::int32_t, 4, Arch >	smmla (simd< std::int32_t, 4, Arch > acc, simd< std::int8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Signed 2x8 times 8x2 matrix multiply-accumulate.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::i8mm) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int8_t, 16, Arch>); })
consteval simd< std::int32_t, 4, Arch >	smmla (simd< std::int32_t, 4, Arch > acc, simd< std::int8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::i8mm))
constexpr simd< std::uint32_t, 4, Arch >	ummla (simd< std::uint32_t, 4, Arch > acc, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Unsigned 2x8 times 8x2 matrix multiply-accumulate.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::i8mm) && requires { sizeof(simd<std::uint32_t, 4, Arch>); sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	ummla (simd< std::uint32_t, 4, Arch > acc, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::i8mm))
constexpr simd< std::int32_t, 4, Arch >	usmmla (simd< std::int32_t, 4, Arch > acc, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Unsigned left matrix times signed right matrix, with signed accumulator.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::i8mm) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::uint8_t, 16, Arch> ); sizeof(simd<std::int8_t, 16, Arch>); })
consteval simd< std::int32_t, 4, Arch >	usmmla (simd< std::int32_t, 4, Arch > acc, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::i8mm))
constexpr simd< std::int32_t, 2, Arch >	usdot (simd< std::int32_t, 2, Arch > acc, simd< std::uint8_t, 8, Arch > a, simd< std::int8_t, 8, Arch > b) noexcept
	Accumulate each corresponding group of four unsigned a bytes times signed b bytes.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::i8mm) && requires { sizeof(simd<std::int32_t, 2, Arch>); sizeof(simd<std::uint8_t, 8, Arch> ); sizeof(simd<std::int8_t, 8, Arch>); })
consteval simd< std::int32_t, 2, Arch >	usdot (simd< std::int32_t, 2, Arch > acc, simd< std::uint8_t, 8, Arch > a, simd< std::int8_t, 8, Arch > b) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::i8mm) && Lane < 2)
constexpr simd< std::int32_t, 2, Arch >	usdot_lane (simd< std::int32_t, 2, Arch > acc, simd< std::uint8_t, 8, Arch > a, simd< std::int8_t, 8, Arch > b) noexcept
	Accumulate each four-byte group of a times b[4Lane..4Lane+3].
template<isa< arm > Arch, unsigned Lane> requires (!Arch.has(arm_feature::i8mm) && Lane < 2 && requires { sizeof(simd<std::int32_t, 2, Arch>); sizeof(simd<std::uint8_t, 8, Arch>); sizeof(simd<std::int8_t, 8, Arch>); })
consteval simd< std::int32_t, 2, Arch >	usdot_lane (simd< std::int32_t, 2, Arch > acc, simd< std::uint8_t, 8, Arch > a, simd< std::int8_t, 8, Arch > b) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::i8mm) && Lane < 2)
constexpr simd< std::int32_t, 2, Arch >	sudot_lane (simd< std::int32_t, 2, Arch > acc, simd< std::int8_t, 8, Arch > a, simd< std::uint8_t, 8, Arch > b) noexcept
	Accumulate each four-byte group of a times b[4Lane..4Lane+3].
template<isa< arm > Arch, unsigned Lane> requires (!Arch.has(arm_feature::i8mm) && Lane < 2 && requires { sizeof(simd<std::int32_t, 2, Arch>); sizeof(simd<std::int8_t, 8, Arch>); sizeof(simd<std::uint8_t, 8, Arch>); })
consteval simd< std::int32_t, 2, Arch >	sudot_lane (simd< std::int32_t, 2, Arch > acc, simd< std::int8_t, 8, Arch > a, simd< std::uint8_t, 8, Arch > b) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::i8mm) && Lane < 4)
constexpr simd< std::int32_t, 2, Arch >	usdot_lane (simd< std::int32_t, 2, Arch > acc, simd< std::uint8_t, 8, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Accumulate each four-byte group of a times b[4Lane..4Lane+3].
template<isa< arm > Arch, unsigned Lane> requires (!Arch.has(arm_feature::i8mm) && Lane < 4 && requires { sizeof(simd<std::int32_t, 2, Arch>); sizeof(simd<std::uint8_t, 8, Arch>); sizeof(simd<std::int8_t, 16, Arch>); })
consteval simd< std::int32_t, 2, Arch >	usdot_lane (simd< std::int32_t, 2, Arch > acc, simd< std::uint8_t, 8, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::i8mm) && Lane < 4)
constexpr simd< std::int32_t, 2, Arch >	sudot_lane (simd< std::int32_t, 2, Arch > acc, simd< std::int8_t, 8, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Accumulate each four-byte group of a times b[4Lane..4Lane+3].
template<isa< arm > Arch, unsigned Lane> requires (!Arch.has(arm_feature::i8mm) && Lane < 4 && requires { sizeof(simd<std::int32_t, 2, Arch>); sizeof(simd<std::int8_t, 8, Arch>); sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::int32_t, 2, Arch >	sudot_lane (simd< std::int32_t, 2, Arch > acc, simd< std::int8_t, 8, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::i8mm))
constexpr simd< std::int32_t, 4, Arch >	usdot (simd< std::int32_t, 4, Arch > acc, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Accumulate each corresponding group of four unsigned a bytes times signed b bytes.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::i8mm) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::uint8_t, 16, Arch> ); sizeof(simd<std::int8_t, 16, Arch>); })
consteval simd< std::int32_t, 4, Arch >	usdot (simd< std::int32_t, 4, Arch > acc, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::i8mm) && Lane < 2)
constexpr simd< std::int32_t, 4, Arch >	usdot_lane (simd< std::int32_t, 4, Arch > acc, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 8, Arch > b) noexcept
	Accumulate each four-byte group of a times b[4Lane..4Lane+3].
template<isa< arm > Arch, unsigned Lane> requires (!Arch.has(arm_feature::i8mm) && Lane < 2 && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd<std::int8_t, 8, Arch>); })
consteval simd< std::int32_t, 4, Arch >	usdot_lane (simd< std::int32_t, 4, Arch > acc, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 8, Arch > b) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::i8mm) && Lane < 2)
constexpr simd< std::int32_t, 4, Arch >	sudot_lane (simd< std::int32_t, 4, Arch > acc, simd< std::int8_t, 16, Arch > a, simd< std::uint8_t, 8, Arch > b) noexcept
	Accumulate each four-byte group of a times b[4Lane..4Lane+3].
template<isa< arm > Arch, unsigned Lane> requires (!Arch.has(arm_feature::i8mm) && Lane < 2 && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int8_t, 16, Arch>); sizeof(simd<std::uint8_t, 8, Arch>); })
consteval simd< std::int32_t, 4, Arch >	sudot_lane (simd< std::int32_t, 4, Arch > acc, simd< std::int8_t, 16, Arch > a, simd< std::uint8_t, 8, Arch > b) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::i8mm) && Lane < 4)
constexpr simd< std::int32_t, 4, Arch >	usdot_lane (simd< std::int32_t, 4, Arch > acc, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Accumulate each four-byte group of a times b[4Lane..4Lane+3].
template<isa< arm > Arch, unsigned Lane> requires (!Arch.has(arm_feature::i8mm) && Lane < 4 && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd<std::int8_t, 16, Arch>); })
consteval simd< std::int32_t, 4, Arch >	usdot_lane (simd< std::int32_t, 4, Arch > acc, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::i8mm) && Lane < 4)
constexpr simd< std::int32_t, 4, Arch >	sudot_lane (simd< std::int32_t, 4, Arch > acc, simd< std::int8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Accumulate each four-byte group of a times b[4Lane..4Lane+3].
template<isa< arm > Arch, unsigned Lane> requires (!Arch.has(arm_feature::i8mm) && Lane < 4 && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int8_t, 16, Arch>); sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::int32_t, 4, Arch >	sudot_lane (simd< std::int32_t, 4, Arch > acc, simd< std::int8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch = NATIVE_BASELINE> requires (Arch.has(arm_feature::jsconv))
constexpr std::int32_t	jcvt (double value) noexcept
	Convert a double using FJCVTZS; requires the jsconv feature and matching compiler target.
template<isa< arm > Arch = NATIVE_BASELINE> requires (!Arch.has(arm_feature::jsconv))
consteval std::int32_t	jcvt (double value) noexcept
	Evaluate constant inputs when the architecture does not permit FJCVTZS.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_signed_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	sqadd (simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Signed saturating lane addition.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_signed_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16) && requires { sizeof(simd<T, N, Arch>); })
consteval simd< T, N, Arch >	sqadd (simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Evaluate constant operands when NEON is absent.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_unsigned_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	uqadd (simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Unsigned saturating lane addition.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_unsigned_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16) && requires { sizeof(simd<T, N, Arch>); })
consteval simd< T, N, Arch >	uqadd (simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Evaluate constant operands when NEON is absent.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_signed_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	sqsub (simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Signed saturating lane subtraction.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_signed_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16) && requires { sizeof(simd<T, N, Arch>); })
consteval simd< T, N, Arch >	sqsub (simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Evaluate constant operands when NEON is absent.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_unsigned_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	uqsub (simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Unsigned saturating lane subtraction.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_unsigned_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16) && requires { sizeof(simd<T, N, Arch>); })
consteval simd< T, N, Arch >	uqsub (simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Evaluate constant operands when NEON is absent.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_signed_v<T> && (sizeof(T) == 2 \|\| sizeof(T) == 4) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	sqdmulh (simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Signed doubled multiply-high, saturating the minimum-times-minimum case.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_signed_v<T> && (sizeof(T) == 2 \|\| sizeof(T) == 4) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16) && requires { sizeof(simd<T, N, Arch>); })
consteval simd< T, N, Arch >	sqdmulh (simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Evaluate constant operands without NEON when the storage shape exists.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_signed_v<T> && (sizeof(T) == 2 \|\| sizeof(T) == 4) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	sqrdmulh (simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Signed doubled multiply-high with rounding before final saturation.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_signed_v<T> && (sizeof(T) == 2 \|\| sizeof(T) == 4) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16) && requires { sizeof(simd<T, N, Arch>); })
consteval simd< T, N, Arch >	sqrdmulh (simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Evaluate constant operands without NEON when the storage shape exists.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_signed_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	sshl (simd< T, N, Arch > a, simd< std::make_signed_t< T >, N, Arch > b) noexcept
	Shift by each count lane's signed low byte; negative counts shift right.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_signed_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16) && requires { sizeof(simd<T, N, Arch>); })
consteval simd< T, N, Arch >	sshl (simd< T, N, Arch > a, simd< std::make_signed_t< T >, N, Arch > b) noexcept
	Evaluate constant operands when NEON is absent.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_signed_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	srshl (simd< T, N, Arch > a, simd< std::make_signed_t< T >, N, Arch > b) noexcept
	Shift by each count lane's signed low byte; negative counts shift right with rounding.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_signed_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16) && requires { sizeof(simd<T, N, Arch>); })
consteval simd< T, N, Arch >	srshl (simd< T, N, Arch > a, simd< std::make_signed_t< T >, N, Arch > b) noexcept
	Evaluate constant operands when NEON is absent.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_signed_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	sqshl (simd< T, N, Arch > a, simd< std::make_signed_t< T >, N, Arch > b) noexcept
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_signed_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16) && requires { sizeof(simd<T, N, Arch>); })
consteval simd< T, N, Arch >	sqshl (simd< T, N, Arch > a, simd< std::make_signed_t< T >, N, Arch > b) noexcept
	Evaluate constant operands when NEON is absent.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_signed_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	sqrshl (simd< T, N, Arch > a, simd< std::make_signed_t< T >, N, Arch > b) noexcept
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_signed_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16) && requires { sizeof(simd<T, N, Arch>); })
consteval simd< T, N, Arch >	sqrshl (simd< T, N, Arch > a, simd< std::make_signed_t< T >, N, Arch > b) noexcept
	Evaluate constant operands when NEON is absent.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_unsigned_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	ushl (simd< T, N, Arch > a, simd< std::make_signed_t< T >, N, Arch > b) noexcept
	Shift by each count lane's signed low byte; negative counts shift right.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_unsigned_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16) && requires { sizeof(simd<T, N, Arch>); })
consteval simd< T, N, Arch >	ushl (simd< T, N, Arch > a, simd< std::make_signed_t< T >, N, Arch > b) noexcept
	Evaluate constant operands when NEON is absent.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_unsigned_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	urshl (simd< T, N, Arch > a, simd< std::make_signed_t< T >, N, Arch > b) noexcept
	Shift by each count lane's signed low byte; negative counts shift right with rounding.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_unsigned_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16) && requires { sizeof(simd<T, N, Arch>); })
consteval simd< T, N, Arch >	urshl (simd< T, N, Arch > a, simd< std::make_signed_t< T >, N, Arch > b) noexcept
	Evaluate constant operands when NEON is absent.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_unsigned_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	uqshl (simd< T, N, Arch > a, simd< std::make_signed_t< T >, N, Arch > b) noexcept
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_unsigned_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16) && requires { sizeof(simd<T, N, Arch>); })
consteval simd< T, N, Arch >	uqshl (simd< T, N, Arch > a, simd< std::make_signed_t< T >, N, Arch > b) noexcept
	Evaluate constant operands when NEON is absent.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_unsigned_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	uqrshl (simd< T, N, Arch > a, simd< std::make_signed_t< T >, N, Arch > b) noexcept
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_unsigned_v<T> && (sizeof(T) <= 8) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16) && requires { sizeof(simd<T, N, Arch>); })
consteval simd< T, N, Arch >	uqrshl (simd< T, N, Arch > a, simd< std::make_signed_t< T >, N, Arch > b) noexcept
	Evaluate constant operands when NEON is absent.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_signed_v<T> && sizeof(T) * N == 16 && (sizeof(T) == 2 \|\| sizeof(T) == 4 \|\| sizeof(T) == 8))
constexpr auto	sqxtn (simd< T, N, Arch > a) noexcept
	Narrow 128 bits with saturation to a 64-bit result.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_signed_v<T> && sizeof(T) * N == 16 && (sizeof(T) == 2 \|\| sizeof(T) == 4 \|\| sizeof(T) == 8) && requires { sizeof(simd<T, N, Arch>); })
consteval auto	sqxtn (simd< T, N, Arch > a) noexcept
	Evaluate constant operands without NEON when storage exists.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_signed_v<T> && sizeof(T) * N == 16 && (sizeof(T) == 2 \|\| sizeof(T) == 4 \|\| sizeof(T) == 8))
constexpr auto	sqxtn_high (simd< std::conditional_t< sizeof(T)==2, std::int8_t, std::conditional_t< sizeof(T)==4, std::int16_t, std::int32_t > >, N, Arch > low, simd< T, N, Arch > a) noexcept
	Narrow with saturation and append above the preserved low half.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_signed_v<T> && sizeof(T) * N == 16 && (sizeof(T) == 2 \|\| sizeof(T) == 4 \|\| sizeof(T) == 8) && requires { sizeof(simd<T, N, Arch>); })
consteval auto	sqxtn_high (simd< std::conditional_t< sizeof(T)==2, std::int8_t, std::conditional_t< sizeof(T)==4, std::int16_t, std::int32_t > >, N, Arch > low, simd< T, N, Arch > a) noexcept
	Evaluate constant operands without NEON when storage exists.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_unsigned_v<T> && sizeof(T) * N == 16 && (sizeof(T) == 2 \|\| sizeof(T) == 4 \|\| sizeof(T) == 8))
constexpr auto	uqxtn (simd< T, N, Arch > a) noexcept
	Narrow 128 bits with saturation to a 64-bit result.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_unsigned_v<T> && sizeof(T) * N == 16 && (sizeof(T) == 2 \|\| sizeof(T) == 4 \|\| sizeof(T) == 8) && requires { sizeof(simd<T, N, Arch>); })
consteval auto	uqxtn (simd< T, N, Arch > a) noexcept
	Evaluate constant operands without NEON when storage exists.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_unsigned_v<T> && sizeof(T) * N == 16 && (sizeof(T) == 2 \|\| sizeof(T) == 4 \|\| sizeof(T) == 8))
constexpr auto	uqxtn_high (simd< std::conditional_t< sizeof(T)==2, std::uint8_t, std::conditional_t< sizeof(T)==4, std::uint16_t, std::uint32_t > >, N, Arch > low, simd< T, N, Arch > a) noexcept
	Narrow with saturation and append above the preserved low half.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_unsigned_v<T> && sizeof(T) * N == 16 && (sizeof(T) == 2 \|\| sizeof(T) == 4 \|\| sizeof(T) == 8) && requires { sizeof(simd<T, N, Arch>); })
consteval auto	uqxtn_high (simd< std::conditional_t< sizeof(T)==2, std::uint8_t, std::conditional_t< sizeof(T)==4, std::uint16_t, std::uint32_t > >, N, Arch > low, simd< T, N, Arch > a) noexcept
	Evaluate constant operands without NEON when storage exists.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_signed_v<T> && sizeof(T) * N == 16 && (sizeof(T) == 2 \|\| sizeof(T) == 4 \|\| sizeof(T) == 8))
constexpr auto	sqxtun (simd< T, N, Arch > a) noexcept
	Narrow 128 bits with saturation to a 64-bit result.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_signed_v<T> && sizeof(T) * N == 16 && (sizeof(T) == 2 \|\| sizeof(T) == 4 \|\| sizeof(T) == 8) && requires { sizeof(simd<T, N, Arch>); })
consteval auto	sqxtun (simd< T, N, Arch > a) noexcept
	Evaluate constant operands without NEON when storage exists.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_signed_v<T> && sizeof(T) * N == 16 && (sizeof(T) == 2 \|\| sizeof(T) == 4 \|\| sizeof(T) == 8))
constexpr auto	sqxtun_high (simd< std::conditional_t< sizeof(T)==2, std::uint8_t, std::conditional_t< sizeof(T)==4, std::uint16_t, std::uint32_t > >, N, Arch > low, simd< T, N, Arch > a) noexcept
	Narrow with saturation and append above the preserved low half.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (!Arch.has(arm_feature::neon) && std::is_signed_v<T> && sizeof(T) * N == 16 && (sizeof(T) == 2 \|\| sizeof(T) == 4 \|\| sizeof(T) == 8) && requires { sizeof(simd<T, N, Arch>); })
consteval auto	sqxtun_high (simd< std::conditional_t< sizeof(T)==2, std::uint8_t, std::conditional_t< sizeof(T)==4, std::uint16_t, std::uint32_t > >, N, Arch > low, simd< T, N, Arch > a) noexcept
	Evaluate constant operands without NEON when storage exists.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && (sizeof(T) <= 4) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	clz (simd< T, N, Arch > a) noexcept
	Count leading zero bits in each lane, including the full width for zero.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && std::is_signed_v<T> && (sizeof(T) <= 4) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	cls (simd< T, N, Arch > a) noexcept
	Count leading sign bits in each lane, excluding the sign bit itself.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && (sizeof(T) == 1) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	rbit (simd< T, N, Arch > a) noexcept
	Reverse the eight bits within each byte lane.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && (sizeof(T) == 1) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	rev16 (simd< T, N, Arch > a) noexcept
	Reverse byte lanes within each 16-bit block.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && (sizeof(T) <= 2) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	rev32 (simd< T, N, Arch > a) noexcept
	Reverse byte or halfword lanes within each 32-bit block.
template<isa< arm > Arch, simd_integer_element T, std::size_t N> requires (Arch.has(arm_feature::neon) && (sizeof(T) <= 4) && (sizeof(T) * N == 8 \|\| sizeof(T) * N == 16))
constexpr simd< T, N, Arch >	rev64 (simd< T, N, Arch > a) noexcept
	Reverse byte, halfword or word lanes within each 64-bit block.
template<isa< arm > Arch = NATIVE_BASELINE> requires (Arch.has(arm_feature::pmull))
constexpr simd< std::uint64_t, 2, Arch >	pmull (std::uint64_t a, std::uint64_t b) noexcept
template<isa< arm > Arch = NATIVE_BASELINE> requires (!Arch.has(arm_feature::pmull) && requires { sizeof(simd<std::uint64_t,2,Arch>); })
consteval simd< std::uint64_t, 2, Arch >	pmull (std::uint64_t a, std::uint64_t b) noexcept
	Evaluate a 64-bit polynomial product at compile time using an available SIMD storage shape.
template<isa< arm > Arch> requires (Arch.has(arm_feature::pmull))
constexpr simd< std::uint64_t, 2, Arch >	pmull2 (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Multiply the high 64-bit polynomial lane of each operand; lower lanes are ignored.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::pmull) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	pmull2 (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::neon))
constexpr simd< std::uint16_t, 8, Arch >	pmull (simd< std::uint8_t, 8, Arch > a, simd< std::uint8_t, 8, Arch > b) noexcept
	Multiply eight pairs of byte polynomials into 16-bit products; requires only NEON.
template<isa< arm > Arch> requires (Arch.has(arm_feature::neon))
constexpr simd< std::uint16_t, 8, Arch >	pmull2 (simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Multiply the high eight byte polynomials into 16-bit products; requires only NEON.
template<isa< arm > Arch = NATIVE_BASELINE, class... T>
void	pmull (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	pmull2 (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch = NATIVE_BASELINE> requires (Arch.has(arm_feature::rdm))
constexpr int16_t	sqrdmlah (int16_t accumulator, int16_t lhs, int16_t rhs) noexcept
	SQRDMLAH: signed 16-bit rounding saturating add.
template<isa< arm > Arch = NATIVE_BASELINE> requires (!Arch.has(arm_feature::rdm))
consteval int16_t	sqrdmlah (int16_t accumulator, int16_t lhs, int16_t rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4)
constexpr int16_t	sqrdmlah_lane (int16_t accumulator, int16_t lhs, simd< std::int16_t, 4, Arch > rhs) noexcept
	SQRDMLAH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::int16_t, 4, Arch>); })
consteval int16_t	sqrdmlah_lane (int16_t accumulator, int16_t lhs, simd< std::int16_t, 4, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 8)
constexpr int16_t	sqrdmlah_lane (int16_t accumulator, int16_t lhs, simd< std::int16_t, 8, Arch > rhs) noexcept
	SQRDMLAH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 8 && requires { sizeof(simd<std::int16_t, 8, Arch>); })
consteval int16_t	sqrdmlah_lane (int16_t accumulator, int16_t lhs, simd< std::int16_t, 8, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::rdm))
constexpr simd< std::int16_t, 4, Arch >	sqrdmlah (simd< std::int16_t, 4, Arch > accumulator, simd< std::int16_t, 4, Arch > lhs, simd< std::int16_t, 4, Arch > rhs) noexcept
	SQRDMLAH: signed 16-bit rounding saturating add.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::rdm) && requires { sizeof(simd<std::int16_t, 4, Arch>); })
consteval simd< std::int16_t, 4, Arch >	sqrdmlah (simd< std::int16_t, 4, Arch > accumulator, simd< std::int16_t, 4, Arch > lhs, simd< std::int16_t, 4, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4)
constexpr simd< std::int16_t, 4, Arch >	sqrdmlah_lane (simd< std::int16_t, 4, Arch > accumulator, simd< std::int16_t, 4, Arch > lhs, simd< std::int16_t, 4, Arch > rhs) noexcept
	SQRDMLAH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::int16_t, 4, Arch>); })
consteval simd< std::int16_t, 4, Arch >	sqrdmlah_lane (simd< std::int16_t, 4, Arch > accumulator, simd< std::int16_t, 4, Arch > lhs, simd< std::int16_t, 4, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 8)
constexpr simd< std::int16_t, 4, Arch >	sqrdmlah_lane (simd< std::int16_t, 4, Arch > accumulator, simd< std::int16_t, 4, Arch > lhs, simd< std::int16_t, 8, Arch > rhs) noexcept
	SQRDMLAH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 8 && requires { sizeof(simd<std::int16_t, 4, Arch>); sizeof(simd <std::int16_t, 8, Arch>); })
consteval simd< std::int16_t, 4, Arch >	sqrdmlah_lane (simd< std::int16_t, 4, Arch > accumulator, simd< std::int16_t, 4, Arch > lhs, simd< std::int16_t, 8, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::rdm))
constexpr simd< std::int16_t, 8, Arch >	sqrdmlah (simd< std::int16_t, 8, Arch > accumulator, simd< std::int16_t, 8, Arch > lhs, simd< std::int16_t, 8, Arch > rhs) noexcept
	SQRDMLAH: signed 16-bit rounding saturating add.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::rdm) && requires { sizeof(simd<std::int16_t, 8, Arch>); })
consteval simd< std::int16_t, 8, Arch >	sqrdmlah (simd< std::int16_t, 8, Arch > accumulator, simd< std::int16_t, 8, Arch > lhs, simd< std::int16_t, 8, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4)
constexpr simd< std::int16_t, 8, Arch >	sqrdmlah_lane (simd< std::int16_t, 8, Arch > accumulator, simd< std::int16_t, 8, Arch > lhs, simd< std::int16_t, 4, Arch > rhs) noexcept
	SQRDMLAH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::int16_t, 8, Arch>); sizeof(simd <std::int16_t, 4, Arch>); })
consteval simd< std::int16_t, 8, Arch >	sqrdmlah_lane (simd< std::int16_t, 8, Arch > accumulator, simd< std::int16_t, 8, Arch > lhs, simd< std::int16_t, 4, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 8)
constexpr simd< std::int16_t, 8, Arch >	sqrdmlah_lane (simd< std::int16_t, 8, Arch > accumulator, simd< std::int16_t, 8, Arch > lhs, simd< std::int16_t, 8, Arch > rhs) noexcept
	SQRDMLAH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 8 && requires { sizeof(simd<std::int16_t, 8, Arch>); })
consteval simd< std::int16_t, 8, Arch >	sqrdmlah_lane (simd< std::int16_t, 8, Arch > accumulator, simd< std::int16_t, 8, Arch > lhs, simd< std::int16_t, 8, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch = NATIVE_BASELINE> requires (Arch.has(arm_feature::rdm))
constexpr int32_t	sqrdmlah (int32_t accumulator, int32_t lhs, int32_t rhs) noexcept
	SQRDMLAH: signed 32-bit rounding saturating add.
template<isa< arm > Arch = NATIVE_BASELINE> requires (!Arch.has(arm_feature::rdm))
consteval int32_t	sqrdmlah (int32_t accumulator, int32_t lhs, int32_t rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 2)
constexpr int32_t	sqrdmlah_lane (int32_t accumulator, int32_t lhs, simd< std::int32_t, 2, Arch > rhs) noexcept
	SQRDMLAH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 2 && requires { sizeof(simd<std::int32_t, 2, Arch>); })
consteval int32_t	sqrdmlah_lane (int32_t accumulator, int32_t lhs, simd< std::int32_t, 2, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4)
constexpr int32_t	sqrdmlah_lane (int32_t accumulator, int32_t lhs, simd< std::int32_t, 4, Arch > rhs) noexcept
	SQRDMLAH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::int32_t, 4, Arch>); })
consteval int32_t	sqrdmlah_lane (int32_t accumulator, int32_t lhs, simd< std::int32_t, 4, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::rdm))
constexpr simd< std::int32_t, 2, Arch >	sqrdmlah (simd< std::int32_t, 2, Arch > accumulator, simd< std::int32_t, 2, Arch > lhs, simd< std::int32_t, 2, Arch > rhs) noexcept
	SQRDMLAH: signed 32-bit rounding saturating add.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::rdm) && requires { sizeof(simd<std::int32_t, 2, Arch>); })
consteval simd< std::int32_t, 2, Arch >	sqrdmlah (simd< std::int32_t, 2, Arch > accumulator, simd< std::int32_t, 2, Arch > lhs, simd< std::int32_t, 2, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 2)
constexpr simd< std::int32_t, 2, Arch >	sqrdmlah_lane (simd< std::int32_t, 2, Arch > accumulator, simd< std::int32_t, 2, Arch > lhs, simd< std::int32_t, 2, Arch > rhs) noexcept
	SQRDMLAH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 2 && requires { sizeof(simd<std::int32_t, 2, Arch>); })
consteval simd< std::int32_t, 2, Arch >	sqrdmlah_lane (simd< std::int32_t, 2, Arch > accumulator, simd< std::int32_t, 2, Arch > lhs, simd< std::int32_t, 2, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4)
constexpr simd< std::int32_t, 2, Arch >	sqrdmlah_lane (simd< std::int32_t, 2, Arch > accumulator, simd< std::int32_t, 2, Arch > lhs, simd< std::int32_t, 4, Arch > rhs) noexcept
	SQRDMLAH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::int32_t, 2, Arch>); sizeof(simd <std::int32_t, 4, Arch>); })
consteval simd< std::int32_t, 2, Arch >	sqrdmlah_lane (simd< std::int32_t, 2, Arch > accumulator, simd< std::int32_t, 2, Arch > lhs, simd< std::int32_t, 4, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::rdm))
constexpr simd< std::int32_t, 4, Arch >	sqrdmlah (simd< std::int32_t, 4, Arch > accumulator, simd< std::int32_t, 4, Arch > lhs, simd< std::int32_t, 4, Arch > rhs) noexcept
	SQRDMLAH: signed 32-bit rounding saturating add.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::rdm) && requires { sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< std::int32_t, 4, Arch >	sqrdmlah (simd< std::int32_t, 4, Arch > accumulator, simd< std::int32_t, 4, Arch > lhs, simd< std::int32_t, 4, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 2)
constexpr simd< std::int32_t, 4, Arch >	sqrdmlah_lane (simd< std::int32_t, 4, Arch > accumulator, simd< std::int32_t, 4, Arch > lhs, simd< std::int32_t, 2, Arch > rhs) noexcept
	SQRDMLAH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 2 && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd <std::int32_t, 2, Arch>); })
consteval simd< std::int32_t, 4, Arch >	sqrdmlah_lane (simd< std::int32_t, 4, Arch > accumulator, simd< std::int32_t, 4, Arch > lhs, simd< std::int32_t, 2, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4)
constexpr simd< std::int32_t, 4, Arch >	sqrdmlah_lane (simd< std::int32_t, 4, Arch > accumulator, simd< std::int32_t, 4, Arch > lhs, simd< std::int32_t, 4, Arch > rhs) noexcept
	SQRDMLAH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< std::int32_t, 4, Arch >	sqrdmlah_lane (simd< std::int32_t, 4, Arch > accumulator, simd< std::int32_t, 4, Arch > lhs, simd< std::int32_t, 4, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch = NATIVE_BASELINE> requires (Arch.has(arm_feature::rdm))
constexpr int16_t	sqrdmlsh (int16_t accumulator, int16_t lhs, int16_t rhs) noexcept
	SQRDMLSH: signed 16-bit rounding saturating subtract.
template<isa< arm > Arch = NATIVE_BASELINE> requires (!Arch.has(arm_feature::rdm))
consteval int16_t	sqrdmlsh (int16_t accumulator, int16_t lhs, int16_t rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4)
constexpr int16_t	sqrdmlsh_lane (int16_t accumulator, int16_t lhs, simd< std::int16_t, 4, Arch > rhs) noexcept
	SQRDMLSH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::int16_t, 4, Arch>); })
consteval int16_t	sqrdmlsh_lane (int16_t accumulator, int16_t lhs, simd< std::int16_t, 4, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 8)
constexpr int16_t	sqrdmlsh_lane (int16_t accumulator, int16_t lhs, simd< std::int16_t, 8, Arch > rhs) noexcept
	SQRDMLSH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 8 && requires { sizeof(simd<std::int16_t, 8, Arch>); })
consteval int16_t	sqrdmlsh_lane (int16_t accumulator, int16_t lhs, simd< std::int16_t, 8, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::rdm))
constexpr simd< std::int16_t, 4, Arch >	sqrdmlsh (simd< std::int16_t, 4, Arch > accumulator, simd< std::int16_t, 4, Arch > lhs, simd< std::int16_t, 4, Arch > rhs) noexcept
	SQRDMLSH: signed 16-bit rounding saturating subtract.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::rdm) && requires { sizeof(simd<std::int16_t, 4, Arch>); })
consteval simd< std::int16_t, 4, Arch >	sqrdmlsh (simd< std::int16_t, 4, Arch > accumulator, simd< std::int16_t, 4, Arch > lhs, simd< std::int16_t, 4, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4)
constexpr simd< std::int16_t, 4, Arch >	sqrdmlsh_lane (simd< std::int16_t, 4, Arch > accumulator, simd< std::int16_t, 4, Arch > lhs, simd< std::int16_t, 4, Arch > rhs) noexcept
	SQRDMLSH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::int16_t, 4, Arch>); })
consteval simd< std::int16_t, 4, Arch >	sqrdmlsh_lane (simd< std::int16_t, 4, Arch > accumulator, simd< std::int16_t, 4, Arch > lhs, simd< std::int16_t, 4, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 8)
constexpr simd< std::int16_t, 4, Arch >	sqrdmlsh_lane (simd< std::int16_t, 4, Arch > accumulator, simd< std::int16_t, 4, Arch > lhs, simd< std::int16_t, 8, Arch > rhs) noexcept
	SQRDMLSH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 8 && requires { sizeof(simd<std::int16_t, 4, Arch>); sizeof(simd <std::int16_t, 8, Arch>); })
consteval simd< std::int16_t, 4, Arch >	sqrdmlsh_lane (simd< std::int16_t, 4, Arch > accumulator, simd< std::int16_t, 4, Arch > lhs, simd< std::int16_t, 8, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::rdm))
constexpr simd< std::int16_t, 8, Arch >	sqrdmlsh (simd< std::int16_t, 8, Arch > accumulator, simd< std::int16_t, 8, Arch > lhs, simd< std::int16_t, 8, Arch > rhs) noexcept
	SQRDMLSH: signed 16-bit rounding saturating subtract.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::rdm) && requires { sizeof(simd<std::int16_t, 8, Arch>); })
consteval simd< std::int16_t, 8, Arch >	sqrdmlsh (simd< std::int16_t, 8, Arch > accumulator, simd< std::int16_t, 8, Arch > lhs, simd< std::int16_t, 8, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4)
constexpr simd< std::int16_t, 8, Arch >	sqrdmlsh_lane (simd< std::int16_t, 8, Arch > accumulator, simd< std::int16_t, 8, Arch > lhs, simd< std::int16_t, 4, Arch > rhs) noexcept
	SQRDMLSH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::int16_t, 8, Arch>); sizeof(simd <std::int16_t, 4, Arch>); })
consteval simd< std::int16_t, 8, Arch >	sqrdmlsh_lane (simd< std::int16_t, 8, Arch > accumulator, simd< std::int16_t, 8, Arch > lhs, simd< std::int16_t, 4, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 8)
constexpr simd< std::int16_t, 8, Arch >	sqrdmlsh_lane (simd< std::int16_t, 8, Arch > accumulator, simd< std::int16_t, 8, Arch > lhs, simd< std::int16_t, 8, Arch > rhs) noexcept
	SQRDMLSH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 8 && requires { sizeof(simd<std::int16_t, 8, Arch>); })
consteval simd< std::int16_t, 8, Arch >	sqrdmlsh_lane (simd< std::int16_t, 8, Arch > accumulator, simd< std::int16_t, 8, Arch > lhs, simd< std::int16_t, 8, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch = NATIVE_BASELINE> requires (Arch.has(arm_feature::rdm))
constexpr int32_t	sqrdmlsh (int32_t accumulator, int32_t lhs, int32_t rhs) noexcept
	SQRDMLSH: signed 32-bit rounding saturating subtract.
template<isa< arm > Arch = NATIVE_BASELINE> requires (!Arch.has(arm_feature::rdm))
consteval int32_t	sqrdmlsh (int32_t accumulator, int32_t lhs, int32_t rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 2)
constexpr int32_t	sqrdmlsh_lane (int32_t accumulator, int32_t lhs, simd< std::int32_t, 2, Arch > rhs) noexcept
	SQRDMLSH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 2 && requires { sizeof(simd<std::int32_t, 2, Arch>); })
consteval int32_t	sqrdmlsh_lane (int32_t accumulator, int32_t lhs, simd< std::int32_t, 2, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4)
constexpr int32_t	sqrdmlsh_lane (int32_t accumulator, int32_t lhs, simd< std::int32_t, 4, Arch > rhs) noexcept
	SQRDMLSH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::int32_t, 4, Arch>); })
consteval int32_t	sqrdmlsh_lane (int32_t accumulator, int32_t lhs, simd< std::int32_t, 4, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::rdm))
constexpr simd< std::int32_t, 2, Arch >	sqrdmlsh (simd< std::int32_t, 2, Arch > accumulator, simd< std::int32_t, 2, Arch > lhs, simd< std::int32_t, 2, Arch > rhs) noexcept
	SQRDMLSH: signed 32-bit rounding saturating subtract.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::rdm) && requires { sizeof(simd<std::int32_t, 2, Arch>); })
consteval simd< std::int32_t, 2, Arch >	sqrdmlsh (simd< std::int32_t, 2, Arch > accumulator, simd< std::int32_t, 2, Arch > lhs, simd< std::int32_t, 2, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 2)
constexpr simd< std::int32_t, 2, Arch >	sqrdmlsh_lane (simd< std::int32_t, 2, Arch > accumulator, simd< std::int32_t, 2, Arch > lhs, simd< std::int32_t, 2, Arch > rhs) noexcept
	SQRDMLSH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 2 && requires { sizeof(simd<std::int32_t, 2, Arch>); })
consteval simd< std::int32_t, 2, Arch >	sqrdmlsh_lane (simd< std::int32_t, 2, Arch > accumulator, simd< std::int32_t, 2, Arch > lhs, simd< std::int32_t, 2, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4)
constexpr simd< std::int32_t, 2, Arch >	sqrdmlsh_lane (simd< std::int32_t, 2, Arch > accumulator, simd< std::int32_t, 2, Arch > lhs, simd< std::int32_t, 4, Arch > rhs) noexcept
	SQRDMLSH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::int32_t, 2, Arch>); sizeof(simd <std::int32_t, 4, Arch>); })
consteval simd< std::int32_t, 2, Arch >	sqrdmlsh_lane (simd< std::int32_t, 2, Arch > accumulator, simd< std::int32_t, 2, Arch > lhs, simd< std::int32_t, 4, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::rdm))
constexpr simd< std::int32_t, 4, Arch >	sqrdmlsh (simd< std::int32_t, 4, Arch > accumulator, simd< std::int32_t, 4, Arch > lhs, simd< std::int32_t, 4, Arch > rhs) noexcept
	SQRDMLSH: signed 32-bit rounding saturating subtract.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::rdm) && requires { sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< std::int32_t, 4, Arch >	sqrdmlsh (simd< std::int32_t, 4, Arch > accumulator, simd< std::int32_t, 4, Arch > lhs, simd< std::int32_t, 4, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 2)
constexpr simd< std::int32_t, 4, Arch >	sqrdmlsh_lane (simd< std::int32_t, 4, Arch > accumulator, simd< std::int32_t, 4, Arch > lhs, simd< std::int32_t, 2, Arch > rhs) noexcept
	SQRDMLSH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 2 && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd <std::int32_t, 2, Arch>); })
consteval simd< std::int32_t, 4, Arch >	sqrdmlsh_lane (simd< std::int32_t, 4, Arch > accumulator, simd< std::int32_t, 4, Arch > lhs, simd< std::int32_t, 2, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4)
constexpr simd< std::int32_t, 4, Arch >	sqrdmlsh_lane (simd< std::int32_t, 4, Arch > accumulator, simd< std::int32_t, 4, Arch > lhs, simd< std::int32_t, 4, Arch > rhs) noexcept
	SQRDMLSH by element: broadcast rhs[Lane] before rounding and saturation.
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::rdm) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< std::int32_t, 4, Arch >	sqrdmlsh_lane (simd< std::int32_t, 4, Arch > accumulator, simd< std::int32_t, 4, Arch > lhs, simd< std::int32_t, 4, Arch > rhs) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha1))
constexpr simd< std::uint32_t, 4, Arch >	sha1c (simd< std::uint32_t, 4, Arch > abcd, std::uint32_t e, simd< std::uint32_t, 4, Arch > wk) noexcept
	Perform four SHA-1 rounds using choice; wk already includes the round constants.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha1) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sha1c (simd< std::uint32_t, 4, Arch > abcd, std::uint32_t e, simd< std::uint32_t, 4, Arch > wk) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha1))
constexpr simd< std::uint32_t, 4, Arch >	sha1p (simd< std::uint32_t, 4, Arch > abcd, std::uint32_t e, simd< std::uint32_t, 4, Arch > wk) noexcept
	Perform four SHA-1 rounds using parity; wk already includes the round constants.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha1) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sha1p (simd< std::uint32_t, 4, Arch > abcd, std::uint32_t e, simd< std::uint32_t, 4, Arch > wk) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha1))
constexpr simd< std::uint32_t, 4, Arch >	sha1m (simd< std::uint32_t, 4, Arch > abcd, std::uint32_t e, simd< std::uint32_t, 4, Arch > wk) noexcept
	Perform four SHA-1 rounds using majority; wk already includes the round constants.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha1) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sha1m (simd< std::uint32_t, 4, Arch > abcd, std::uint32_t e, simd< std::uint32_t, 4, Arch > wk) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch = NATIVE_BASELINE> requires (Arch.has(arm_feature::sha1))
constexpr std::uint32_t	sha1h (std::uint32_t a) noexcept
	Rotate a SHA-1 state word right by two bits; Arch defaults to the module baseline.
template<isa< arm > Arch = NATIVE_BASELINE> requires (!Arch.has(arm_feature::sha1))
consteval std::uint32_t	sha1h (std::uint32_t a) noexcept
	Evaluate the SHA-1 rotation at compile time without requiring SHA instructions.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha1))
constexpr simd< std::uint32_t, 4, Arch >	sha1su0 (simd< std::uint32_t, 4, Arch > w0_3, simd< std::uint32_t, 4, Arch > w4_7, simd< std::uint32_t, 4, Arch > w8_11) noexcept
	Compute the first part of the SHA-1 schedule update for four consecutive words.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha1) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sha1su0 (simd< std::uint32_t, 4, Arch > w0_3, simd< std::uint32_t, 4, Arch > w4_7, simd< std::uint32_t, 4, Arch > w8_11) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha1))
constexpr simd< std::uint32_t, 4, Arch >	sha1su1 (simd< std::uint32_t, 4, Arch > partial, simd< std::uint32_t, 4, Arch > w12_15) noexcept
	Finish the four-word SHA-1 schedule update from sha1su0 and words 12 through 15.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha1) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sha1su1 (simd< std::uint32_t, 4, Arch > partial, simd< std::uint32_t, 4, Arch > w12_15) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha2))
constexpr simd< std::uint32_t, 4, Arch >	sha256h (simd< std::uint32_t, 4, Arch > abcd, simd< std::uint32_t, 4, Arch > efgh, simd< std::uint32_t, 4, Arch > wk) noexcept
	Return a,b,c,d after four SHA-256 rounds; wk includes round constants.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha2) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sha256h (simd< std::uint32_t, 4, Arch > abcd, simd< std::uint32_t, 4, Arch > efgh, simd< std::uint32_t, 4, Arch > wk) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha2))
constexpr simd< std::uint32_t, 4, Arch >	sha256h2 (simd< std::uint32_t, 4, Arch > efgh, simd< std::uint32_t, 4, Arch > abcd, simd< std::uint32_t, 4, Arch > wk) noexcept
	Return e,f,g,h after four SHA-256 rounds; abcd is the state before those rounds.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha2) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sha256h2 (simd< std::uint32_t, 4, Arch > efgh, simd< std::uint32_t, 4, Arch > abcd, simd< std::uint32_t, 4, Arch > wk) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha2))
constexpr simd< std::uint32_t, 4, Arch >	sha256su0 (simd< std::uint32_t, 4, Arch > w0_3, simd< std::uint32_t, 4, Arch > w4_7) noexcept
	Compute the first part of a four-word SHA-256 schedule update.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha2) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sha256su0 (simd< std::uint32_t, 4, Arch > w0_3, simd< std::uint32_t, 4, Arch > w4_7) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha2))
constexpr simd< std::uint32_t, 4, Arch >	sha256su1 (simd< std::uint32_t, 4, Arch > partial, simd< std::uint32_t, 4, Arch > w8_11, simd< std::uint32_t, 4, Arch > w12_15) noexcept
	Finish the four-word SHA-256 schedule update from sha256su0.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha2) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sha256su1 (simd< std::uint32_t, 4, Arch > partial, simd< std::uint32_t, 4, Arch > w8_11, simd< std::uint32_t, 4, Arch > w12_15) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha512))
constexpr simd< std::uint64_t, 2, Arch >	sha512h (simd< std::uint64_t, 2, Arch > sum, simd< std::uint64_t, 2, Arch > fg, simd< std::uint64_t, 2, Arch > de) noexcept
	Apply SHA512H to prepared round sums and packed f,g and d,e state.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha512) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	sha512h (simd< std::uint64_t, 2, Arch > sum, simd< std::uint64_t, 2, Arch > fg, simd< std::uint64_t, 2, Arch > de) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha512))
constexpr simd< std::uint64_t, 2, Arch >	sha512h2 (simd< std::uint64_t, 2, Arch > sum_ab, simd< std::uint64_t, 2, Arch > c_, simd< std::uint64_t, 2, Arch > ab) noexcept
	Apply SHA512H2 to prepared sums, c, and the packed a,b state.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha512) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	sha512h2 (simd< std::uint64_t, 2, Arch > sum_ab, simd< std::uint64_t, 2, Arch > c_, simd< std::uint64_t, 2, Arch > ab) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha512))
constexpr simd< std::uint64_t, 2, Arch >	sha512su0 (simd< std::uint64_t, 2, Arch > w0_1, simd< std::uint64_t, 2, Arch > w2_) noexcept
	Compute the first part of a two-word SHA-512 schedule update.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha512) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	sha512su0 (simd< std::uint64_t, 2, Arch > w0_1, simd< std::uint64_t, 2, Arch > w2_) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha512))
constexpr simd< std::uint64_t, 2, Arch >	sha512su1 (simd< std::uint64_t, 2, Arch > partial, simd< std::uint64_t, 2, Arch > w14_15, simd< std::uint64_t, 2, Arch > w9_10) noexcept
	Finish the two-word SHA-512 schedule update from sha512su0.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha512) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	sha512su1 (simd< std::uint64_t, 2, Arch > partial, simd< std::uint64_t, 2, Arch > w14_15, simd< std::uint64_t, 2, Arch > w9_10) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3))
constexpr simd< std::uint8_t, 16, Arch >	eor3 (simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b, simd< std::uint8_t, 16, Arch > c) noexcept
	Return a XOR b XOR c for every bit.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	eor3 (simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b, simd< std::uint8_t, 16, Arch > c) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3))
constexpr simd< std::uint16_t, 8, Arch >	eor3 (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > c) noexcept
	Return a XOR b XOR c for every bit.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	eor3 (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > c) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3))
constexpr simd< std::uint32_t, 4, Arch >	eor3 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Return a XOR b XOR c for every bit.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	eor3 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3))
constexpr simd< std::uint64_t, 2, Arch >	eor3 (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > c) noexcept
	Return a XOR b XOR c for every bit.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	eor3 (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > c) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3))
constexpr simd< std::int8_t, 16, Arch >	eor3 (simd< std::int8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b, simd< std::int8_t, 16, Arch > c) noexcept
	Return a XOR b XOR c for every bit.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::int8_t, 16, Arch>); })
consteval simd< std::int8_t, 16, Arch >	eor3 (simd< std::int8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b, simd< std::int8_t, 16, Arch > c) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3))
constexpr simd< std::int16_t, 8, Arch >	eor3 (simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b, simd< std::int16_t, 8, Arch > c) noexcept
	Return a XOR b XOR c for every bit.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::int16_t, 8, Arch>); })
consteval simd< std::int16_t, 8, Arch >	eor3 (simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b, simd< std::int16_t, 8, Arch > c) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3))
constexpr simd< std::int32_t, 4, Arch >	eor3 (simd< std::int32_t, 4, Arch > a, simd< std::int32_t, 4, Arch > b, simd< std::int32_t, 4, Arch > c) noexcept
	Return a XOR b XOR c for every bit.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< std::int32_t, 4, Arch >	eor3 (simd< std::int32_t, 4, Arch > a, simd< std::int32_t, 4, Arch > b, simd< std::int32_t, 4, Arch > c) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3))
constexpr simd< std::int64_t, 2, Arch >	eor3 (simd< std::int64_t, 2, Arch > a, simd< std::int64_t, 2, Arch > b, simd< std::int64_t, 2, Arch > c) noexcept
	Return a XOR b XOR c for every bit.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::int64_t, 2, Arch>); })
consteval simd< std::int64_t, 2, Arch >	eor3 (simd< std::int64_t, 2, Arch > a, simd< std::int64_t, 2, Arch > b, simd< std::int64_t, 2, Arch > c) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3))
constexpr simd< std::uint8_t, 16, Arch >	bcax (simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b, simd< std::uint8_t, 16, Arch > c) noexcept
	Return a XOR (b AND NOT c) for every bit.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	bcax (simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b, simd< std::uint8_t, 16, Arch > c) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3))
constexpr simd< std::uint16_t, 8, Arch >	bcax (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > c) noexcept
	Return a XOR (b AND NOT c) for every bit.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	bcax (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > c) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3))
constexpr simd< std::uint32_t, 4, Arch >	bcax (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Return a XOR (b AND NOT c) for every bit.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	bcax (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3))
constexpr simd< std::uint64_t, 2, Arch >	bcax (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > c) noexcept
	Return a XOR (b AND NOT c) for every bit.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	bcax (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > c) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3))
constexpr simd< std::int8_t, 16, Arch >	bcax (simd< std::int8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b, simd< std::int8_t, 16, Arch > c) noexcept
	Return a XOR (b AND NOT c) for every bit.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::int8_t, 16, Arch>); })
consteval simd< std::int8_t, 16, Arch >	bcax (simd< std::int8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b, simd< std::int8_t, 16, Arch > c) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3))
constexpr simd< std::int16_t, 8, Arch >	bcax (simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b, simd< std::int16_t, 8, Arch > c) noexcept
	Return a XOR (b AND NOT c) for every bit.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::int16_t, 8, Arch>); })
consteval simd< std::int16_t, 8, Arch >	bcax (simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b, simd< std::int16_t, 8, Arch > c) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3))
constexpr simd< std::int32_t, 4, Arch >	bcax (simd< std::int32_t, 4, Arch > a, simd< std::int32_t, 4, Arch > b, simd< std::int32_t, 4, Arch > c) noexcept
	Return a XOR (b AND NOT c) for every bit.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< std::int32_t, 4, Arch >	bcax (simd< std::int32_t, 4, Arch > a, simd< std::int32_t, 4, Arch > b, simd< std::int32_t, 4, Arch > c) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3))
constexpr simd< std::int64_t, 2, Arch >	bcax (simd< std::int64_t, 2, Arch > a, simd< std::int64_t, 2, Arch > b, simd< std::int64_t, 2, Arch > c) noexcept
	Return a XOR (b AND NOT c) for every bit.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::int64_t, 2, Arch>); })
consteval simd< std::int64_t, 2, Arch >	bcax (simd< std::int64_t, 2, Arch > a, simd< std::int64_t, 2, Arch > b, simd< std::int64_t, 2, Arch > c) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3))
constexpr simd< std::uint64_t, 2, Arch >	rax1 (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Return a XOR rotate_left(b, 1) in each 64-bit lane.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	rax1 (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, unsigned Rotate> requires (Arch.has(arm_feature::sha3) && Rotate < 64)
constexpr simd< std::uint64_t, 2, Arch >	xar (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Rotate a XOR b right by Rotate bits in each 64-bit lane; Rotate is in [0, 63].
template<isa< arm > Arch, unsigned Rotate> requires (!Arch.has(arm_feature::sha3) && Rotate < 64 && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	xar (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Evaluate constant operands without the instruction feature.
template<isa< arm > Arch, class... T>
void	sha1c (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	sha1p (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	sha1m (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch = NATIVE_BASELINE, class... T>
void	sha1h (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	sha1su0 (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	sha1su1 (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	sha256h (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	sha256h2 (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	sha256su0 (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	sha256su1 (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	sha512h (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	sha512h2 (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	sha512su0 (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	sha512su1 (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	eor3 (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	bcax (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, class... T>
void	rax1 (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch, unsigned Rotate, class... T>
void	xar (T...)=delete
	Reject unsupported argument shapes or unavailable instruction features.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sm3))
constexpr simd< std::uint32_t, 4, Arch >	sm3ss1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Rotate and add the lane-three inputs; return SS1 in lane three and zero elsewhere.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sm3) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sm3ss1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Evaluate constant operands without the SM3 instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::sm3) && Lane >= 0 && Lane < 4)
constexpr simd< std::uint32_t, 4, Arch >	sm3tt1a (simd< std::uint32_t, 4, Arch > state, simd< std::uint32_t, 4, Arch > ss1, simd< std::uint32_t, 4, Arch > words) noexcept
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::sm3) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sm3tt1a (simd< std::uint32_t, 4, Arch > state, simd< std::uint32_t, 4, Arch > ss1, simd< std::uint32_t, 4, Arch > words) noexcept
	Evaluate constant operands without the SM3 instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::sm3) && Lane >= 0 && Lane < 4)
constexpr simd< std::uint32_t, 4, Arch >	sm3tt1b (simd< std::uint32_t, 4, Arch > state, simd< std::uint32_t, 4, Arch > ss1, simd< std::uint32_t, 4, Arch > words) noexcept
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::sm3) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sm3tt1b (simd< std::uint32_t, 4, Arch > state, simd< std::uint32_t, 4, Arch > ss1, simd< std::uint32_t, 4, Arch > words) noexcept
	Evaluate constant operands without the SM3 instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::sm3) && Lane >= 0 && Lane < 4)
constexpr simd< std::uint32_t, 4, Arch >	sm3tt2a (simd< std::uint32_t, 4, Arch > state, simd< std::uint32_t, 4, Arch > ss1, simd< std::uint32_t, 4, Arch > words) noexcept
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::sm3) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sm3tt2a (simd< std::uint32_t, 4, Arch > state, simd< std::uint32_t, 4, Arch > ss1, simd< std::uint32_t, 4, Arch > words) noexcept
	Evaluate constant operands without the SM3 instruction feature.
template<isa< arm > Arch, int Lane> requires (Arch.has(arm_feature::sm3) && Lane >= 0 && Lane < 4)
constexpr simd< std::uint32_t, 4, Arch >	sm3tt2b (simd< std::uint32_t, 4, Arch > state, simd< std::uint32_t, 4, Arch > ss1, simd< std::uint32_t, 4, Arch > words) noexcept
template<isa< arm > Arch, int Lane> requires (!Arch.has(arm_feature::sm3) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sm3tt2b (simd< std::uint32_t, 4, Arch > state, simd< std::uint32_t, 4, Arch > ss1, simd< std::uint32_t, 4, Arch > words) noexcept
	Evaluate constant operands without the SM3 instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sm3))
constexpr simd< std::uint32_t, 4, Arch >	sm3partw1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Compute the first four-word SM3 message-schedule update, including lane-zero feedback.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sm3) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sm3partw1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Evaluate constant operands without the SM3 instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sm3))
constexpr simd< std::uint32_t, 4, Arch >	sm3partw2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Finish the four-word SM3 schedule update with the remaining XOR and rotation terms.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sm3) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sm3partw2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Evaluate constant operands without the SM3 instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sm4))
constexpr simd< std::uint32_t, 4, Arch >	sm4e (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Perform four SM4 data rounds with state words and successive round keys in ascending lanes.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sm4) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sm4e (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Evaluate constant operands without the SM4 instruction feature.
template<isa< arm > Arch> requires (Arch.has(arm_feature::sm4))
constexpr simd< std::uint32_t, 4, Arch >	sm4ekey (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
template<isa< arm > Arch> requires (!Arch.has(arm_feature::sm4) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sm4ekey (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Evaluate constant operands without the SM4 instruction feature.
unique_str	dup (char const *str) noexcept
constexpr fp16	operator""_fp16 (long double v) noexcept
	Round a literal through binary32 to fp16.
constexpr bf16	operator""_bf16 (long double v) noexcept
	Round a literal through binary32 to bf16.
constexpr bf16	fast_to_bf16 (float f) noexcept
constexpr bf16	fast_to_bf16 (bf16 f) noexcept
	Return an already converted bfloat16 unchanged.
template<typename T>
constexpr bool	cmp_unord (T a, T b) noexcept(noexcept(isnan(a)\|\|isnan(b)))
	Return true if either argument is NaN.
template<typename T>
constexpr bool	cmp_ord (T a, T b) noexcept(noexcept(!isnan(a) &&!isnan(b)))
	Return true if neither argument is NaN.
template<one_of_t< float, double > T>
constexpr T	scalef (T x, T y) noexcept
template<CMPINT imm8, typename T> requires (one_of_t<T, uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t> && (std::size_t(imm8) < 8uz))
constexpr bool	cmpint (T a, T b) noexcept
template<CMP imm8, typename T> requires (one_of_t<T, float, double> && (std::size_t(imm8) < 32uz))
constexpr bool	cmp (T a, T b) noexcept
template bool	cmp_unord (float, float)
	Return true if either argument is NaN.
template bool	cmp_unord (double, double)
	Return true if either argument is NaN.
template bool	cmp_ord (float, float)
	Return true if neither argument is NaN.
template bool	cmp_ord (double, double)
	Return true if neither argument is NaN.
template float	scalef (float, float) noexcept
	Scale by a power of two after truncating the exponent toward zero.
template double	scalef (double, double) noexcept
	Scale by a power of two after truncating the exponent toward zero.
template<std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) &&(N == 8 \|\| N == 16 \|\| N == 32)
constexpr simd< float, N/2, Arch >	dot2 (simd< bf16, N, Arch > a, simd< bf16, N, Arch > b, simd< float, N/2, Arch > accumulator) noexcept
template<::native::isa<> Arch> requires (::native::avx512 <= Arch )
constexpr simd< fp16, 32, Arch >	fma (simd< fp16, 32, Arch > a, simd< fp16, 32, Arch > b, simd< fp16, 32, Arch > c) noexcept
template<::native::isa<> Arch> requires (::native::avx512 <= Arch )
constexpr simd< float, 4, Arch >	dot2 (simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b, simd< float, 4, Arch > accumulator) noexcept
template<::native::isa<> Arch> requires (::native::avx512 <= Arch )
constexpr simd< fp16, 8, Arch >	fma (simd< fp16, 8, Arch > a, simd< fp16, 8, Arch > b, simd< fp16, 8, Arch > c) noexcept
template<detail::static_string_literal Text>
consteval auto	operator""_ss () noexcept
template<detail::static_string_literal Text> requires std::same_as<typename decltype(Text)::char_type, char>
consteval static_c_string	operator""_scs () noexcept
std::string_view	type_of (auto const &t)
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< std::uint8_t, 16, Arch >	i8x16_relaxed_swizzle (simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Select bytes; out-of-range indices have relaxed semantics.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	i8x16_relaxed_swizzle (simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< std::int32_t, 4, Arch >	i32x4_relaxed_trunc_f32x4 (simd< float, 4, Arch > a) noexcept
	Truncate toward zero; invalid lanes may differ from saturation.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< std::int32_t, 4, Arch >	i32x4_relaxed_trunc_f32x4 (simd< float, 4, Arch > a) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< std::uint32_t, 4, Arch >	u32x4_relaxed_trunc_f32x4 (simd< float, 4, Arch > a) noexcept
	Truncate toward zero; invalid lanes may differ from saturation.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	u32x4_relaxed_trunc_f32x4 (simd< float, 4, Arch > a) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< std::int32_t, 4, Arch >	i32x4_relaxed_trunc_f64x2_zero (simd< double, 2, Arch > a) noexcept
	Truncate toward zero; invalid lanes may differ from saturation.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< std::int32_t, 4, Arch >	i32x4_relaxed_trunc_f64x2_zero (simd< double, 2, Arch > a) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< std::uint32_t, 4, Arch >	u32x4_relaxed_trunc_f64x2_zero (simd< double, 2, Arch > a) noexcept
	Truncate toward zero; invalid lanes may differ from saturation.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	u32x4_relaxed_trunc_f64x2_zero (simd< double, 2, Arch > a) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< float, 4, Arch >	f32x4_relaxed_madd (simd< float, 4, Arch > a, simd< float, 4, Arch > b, simd< float, 4, Arch > c) noexcept
	Compute a * b + c with fused or separate rounding.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<float, 4, Arch>); })
consteval simd< float, 4, Arch >	f32x4_relaxed_madd (simd< float, 4, Arch > a, simd< float, 4, Arch > b, simd< float, 4, Arch > c) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< float, 4, Arch >	f32x4_relaxed_nmadd (simd< float, 4, Arch > a, simd< float, 4, Arch > b, simd< float, 4, Arch > c) noexcept
	Compute -(a * b) + c with fused or separate rounding.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<float, 4, Arch>); })
consteval simd< float, 4, Arch >	f32x4_relaxed_nmadd (simd< float, 4, Arch > a, simd< float, 4, Arch > b, simd< float, 4, Arch > c) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< double, 2, Arch >	f64x2_relaxed_madd (simd< double, 2, Arch > a, simd< double, 2, Arch > b, simd< double, 2, Arch > c) noexcept
	Compute a * b + c with fused or separate rounding.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<double, 2, Arch>); })
consteval simd< double, 2, Arch >	f64x2_relaxed_madd (simd< double, 2, Arch > a, simd< double, 2, Arch > b, simd< double, 2, Arch > c) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< double, 2, Arch >	f64x2_relaxed_nmadd (simd< double, 2, Arch > a, simd< double, 2, Arch > b, simd< double, 2, Arch > c) noexcept
	Compute -(a * b) + c with fused or separate rounding.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<double, 2, Arch>); })
consteval simd< double, 2, Arch >	f64x2_relaxed_nmadd (simd< double, 2, Arch > a, simd< double, 2, Arch > b, simd< double, 2, Arch > c) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< std::uint8_t, 16, Arch >	i8x16_relaxed_laneselect (simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b, simd< std::uint8_t, 16, Arch > c) noexcept
	Select with mask c; partial masks permit bit or sign-bit lane selection.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	i8x16_relaxed_laneselect (simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b, simd< std::uint8_t, 16, Arch > c) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< std::uint16_t, 8, Arch >	i16x8_relaxed_laneselect (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > c) noexcept
	Select with mask c; partial masks permit bit or sign-bit lane selection.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	i16x8_relaxed_laneselect (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > c) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< std::uint32_t, 4, Arch >	i32x4_relaxed_laneselect (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Select with mask c; partial masks permit bit or sign-bit lane selection.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	i32x4_relaxed_laneselect (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< std::uint64_t, 2, Arch >	i64x2_relaxed_laneselect (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > c) noexcept
	Select with mask c; partial masks permit bit or sign-bit lane selection.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	i64x2_relaxed_laneselect (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > c) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< float, 4, Arch >	f32x4_relaxed_min (simd< float, 4, Arch > a, simd< float, 4, Arch > b) noexcept
	Minimum with relaxed NaN and signed-zero selection.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<float, 4, Arch>); })
consteval simd< float, 4, Arch >	f32x4_relaxed_min (simd< float, 4, Arch > a, simd< float, 4, Arch > b) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< float, 4, Arch >	f32x4_relaxed_max (simd< float, 4, Arch > a, simd< float, 4, Arch > b) noexcept
	Maximum with relaxed NaN and signed-zero selection.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<float, 4, Arch>); })
consteval simd< float, 4, Arch >	f32x4_relaxed_max (simd< float, 4, Arch > a, simd< float, 4, Arch > b) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< double, 2, Arch >	f64x2_relaxed_min (simd< double, 2, Arch > a, simd< double, 2, Arch > b) noexcept
	Minimum with relaxed NaN and signed-zero selection.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<double, 2, Arch>); })
consteval simd< double, 2, Arch >	f64x2_relaxed_min (simd< double, 2, Arch > a, simd< double, 2, Arch > b) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< double, 2, Arch >	f64x2_relaxed_max (simd< double, 2, Arch > a, simd< double, 2, Arch > b) noexcept
	Maximum with relaxed NaN and signed-zero selection.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<double, 2, Arch>); })
consteval simd< double, 2, Arch >	f64x2_relaxed_max (simd< double, 2, Arch > a, simd< double, 2, Arch > b) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< std::int16_t, 8, Arch >	i16x8_relaxed_q15mulr (simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	Rounded Q15 product; the overflowing -32768 squared case is relaxed.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<std::int16_t, 8, Arch>); })
consteval simd< std::int16_t, 8, Arch >	i16x8_relaxed_q15mulr (simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< std::int16_t, 8, Arch >	i16x8_relaxed_dot_i8x16_i7x16 (simd< std::int8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Pairwise signed-byte dot product; high bits of b have relaxed semantics.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<std::int16_t, 8, Arch>); })
consteval simd< std::int16_t, 8, Arch >	i16x8_relaxed_dot_i8x16_i7x16 (simd< std::int8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< wasm > Arch> requires (Arch.has(wasm_feature::relaxed_simd))
constexpr simd< std::int32_t, 4, Arch >	i32x4_relaxed_dot_i8x16_i7x16_add (simd< std::int8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b, simd< std::int32_t, 4, Arch > c) noexcept
	Accumulate two adjacent relaxed dot pairs into c modulo 32 bits.
template<isa< wasm > Arch> requires (!Arch.has(wasm_feature::relaxed_simd) && requires { sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< std::int32_t, 4, Arch >	i32x4_relaxed_dot_i8x16_i7x16_add (simd< std::int8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b, simd< std::int32_t, 4, Arch > c) noexcept
	Evaluate constant operands without the relaxed SIMD instruction feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::adx))
constexpr std::uint8_t	addcarryx (std::uint8_t carry, std::uint32_t a, std::uint32_t b, std::uint32_t *result) noexcept
	Add 32-bit operands with carry, writing the modular result.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::adx))
consteval std::uint8_t	addcarryx (std::uint8_t carry, std::uint32_t a, std::uint32_t b, std::uint32_t *result) noexcept
	Constant 32-bit addition with carry without ADX.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::adx))
constexpr std::uint8_t	addcarryx (std::uint8_t carry, std::uint64_t a, std::uint64_t b, std::uint64_t *result) noexcept
	Add 64-bit operands with carry, writing the modular result.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::adx))
consteval std::uint8_t	addcarryx (std::uint8_t carry, std::uint64_t a, std::uint64_t b, std::uint64_t *result) noexcept
	Constant 64-bit addition with carry without ADX.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::aes))
constexpr simd< std::uint8_t, 16, Arch >	aesenc (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > round_key) noexcept
	Apply ShiftRows, SubBytes, MixColumns and then AddRoundKey.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::aes) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	aesenc (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > round_key) noexcept
	Evaluate constant operands without the AES instruction feature.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::aes))
constexpr simd< std::uint8_t, 16, Arch >	aesenclast (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > round_key) noexcept
	Apply ShiftRows, SubBytes and then AddRoundKey for the final encryption round.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::aes) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	aesenclast (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > round_key) noexcept
	Evaluate constant operands without the AES instruction feature.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::aes))
constexpr simd< std::uint8_t, 16, Arch >	aesdec (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > round_key) noexcept
	Apply inverse ShiftRows, inverse SubBytes, inverse MixColumns and then AddRoundKey.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::aes) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	aesdec (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > round_key) noexcept
	Evaluate constant operands without the AES instruction feature.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::aes))
constexpr simd< std::uint8_t, 16, Arch >	aesdeclast (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > round_key) noexcept
	Apply inverse ShiftRows, inverse SubBytes and then AddRoundKey for the final decryption round.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::aes) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	aesdeclast (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > round_key) noexcept
	Evaluate constant operands without the AES instruction feature.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::aes))
constexpr simd< std::uint8_t, 16, Arch >	aesimc (simd< std::uint8_t, 16, Arch > state) noexcept
	Apply inverse MixColumns to the four state columns.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::aes) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	aesimc (simd< std::uint8_t, 16, Arch > state) noexcept
	Evaluate constant operands without the AES instruction feature.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::aes) && Imm8 <= 255)
constexpr simd< std::uint8_t, 16, Arch >	aeskeygenassist (simd< std::uint8_t, 16, Arch > state) noexcept
template<isa< x86 > Arch, unsigned Imm8> requires (!Arch.has(x86_feature::aes) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	aeskeygenassist (simd< std::uint8_t, 16, Arch > state) noexcept
	Evaluate constant operands without the AES instruction feature.
template<isa< x86 > Arch, class... Args>
void	aesenc (Args...)=delete
	Reject mixed tags, wrong element types and implicit register conversions.
template<isa< x86 > Arch, class... Args>
void	aesenclast (Args...)=delete
	Reject mixed tags, wrong element types and implicit register conversions.
template<isa< x86 > Arch, class... Args>
void	aesdec (Args...)=delete
	Reject mixed tags, wrong element types and implicit register conversions.
template<isa< x86 > Arch, class... Args>
void	aesdeclast (Args...)=delete
	Reject mixed tags, wrong element types and implicit register conversions.
template<isa< x86 > Arch, class... Args>
void	aesimc (Args...)=delete
	Reject mixed tags, wrong element types and implicit register conversions.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	aeskeygenassist (Args...)=delete
	Reject mixed tags, wrong element types and implicit register conversions.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	vpconflictd (simd< std::uint32_t, 4, Arch > value) noexcept
	For each 32-bit lane, set bit j when earlier source lane j is equal.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	mask_vpconflictd (simd< std::uint32_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > value) noexcept
	Inactive destination lanes retain source; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	maskz_vpconflictd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > value) noexcept
	Inactive destination lanes become zero; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	vplzcntd (simd< std::uint32_t, 4, Arch > value) noexcept
	Count leading zeros in each 32-bit lane; zero yields 32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	mask_vplzcntd (simd< std::uint32_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > value) noexcept
	Inactive destination lanes retain source; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	maskz_vplzcntd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > value) noexcept
	Inactive destination lanes become zero; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	vpconflictq (simd< std::uint64_t, 2, Arch > value) noexcept
	For each 64-bit lane, set bit j when earlier source lane j is equal.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	mask_vpconflictq (simd< std::uint64_t, 2, Arch > source, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > value) noexcept
	Inactive destination lanes retain source; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	maskz_vpconflictq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > value) noexcept
	Inactive destination lanes become zero; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	vplzcntq (simd< std::uint64_t, 2, Arch > value) noexcept
	Count leading zeros in each 64-bit lane; zero yields 64.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	mask_vplzcntq (simd< std::uint64_t, 2, Arch > source, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > value) noexcept
	Inactive destination lanes retain source; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	maskz_vplzcntq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > value) noexcept
	Inactive destination lanes become zero; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	vpconflictd (simd< std::uint32_t, 8, Arch > value) noexcept
	For each 32-bit lane, set bit j when earlier source lane j is equal.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	mask_vpconflictd (simd< std::uint32_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > value) noexcept
	Inactive destination lanes retain source; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	maskz_vpconflictd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > value) noexcept
	Inactive destination lanes become zero; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	vplzcntd (simd< std::uint32_t, 8, Arch > value) noexcept
	Count leading zeros in each 32-bit lane; zero yields 32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	mask_vplzcntd (simd< std::uint32_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > value) noexcept
	Inactive destination lanes retain source; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	maskz_vplzcntd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > value) noexcept
	Inactive destination lanes become zero; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	vpconflictq (simd< std::uint64_t, 4, Arch > value) noexcept
	For each 64-bit lane, set bit j when earlier source lane j is equal.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	mask_vpconflictq (simd< std::uint64_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > value) noexcept
	Inactive destination lanes retain source; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	maskz_vpconflictq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > value) noexcept
	Inactive destination lanes become zero; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	vplzcntq (simd< std::uint64_t, 4, Arch > value) noexcept
	Count leading zeros in each 64-bit lane; zero yields 64.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	mask_vplzcntq (simd< std::uint64_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > value) noexcept
	Inactive destination lanes retain source; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	maskz_vplzcntq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > value) noexcept
	Inactive destination lanes become zero; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint32_t, 16, Arch >	vpconflictd (simd< std::uint32_t, 16, Arch > value) noexcept
	For each 32-bit lane, set bit j when earlier source lane j is equal.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint32_t, 16, Arch >	mask_vpconflictd (simd< std::uint32_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > value) noexcept
	Inactive destination lanes retain source; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint32_t, 16, Arch >	maskz_vpconflictd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > value) noexcept
	Inactive destination lanes become zero; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint32_t, 16, Arch >	vplzcntd (simd< std::uint32_t, 16, Arch > value) noexcept
	Count leading zeros in each 32-bit lane; zero yields 32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint32_t, 16, Arch >	mask_vplzcntd (simd< std::uint32_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > value) noexcept
	Inactive destination lanes retain source; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint32_t, 16, Arch >	maskz_vplzcntd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > value) noexcept
	Inactive destination lanes become zero; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint64_t, 8, Arch >	vpconflictq (simd< std::uint64_t, 8, Arch > value) noexcept
	For each 64-bit lane, set bit j when earlier source lane j is equal.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint64_t, 8, Arch >	mask_vpconflictq (simd< std::uint64_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > value) noexcept
	Inactive destination lanes retain source; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint64_t, 8, Arch >	maskz_vpconflictq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > value) noexcept
	Inactive destination lanes become zero; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint64_t, 8, Arch >	vplzcntq (simd< std::uint64_t, 8, Arch > value) noexcept
	Count leading zeros in each 64-bit lane; zero yields 64.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint64_t, 8, Arch >	mask_vplzcntq (simd< std::uint64_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > value) noexcept
	Inactive destination lanes retain source; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint64_t, 8, Arch >	maskz_vplzcntq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > value) noexcept
	Inactive destination lanes become zero; zero input yields the lane width.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	vpconflictd (simd< std::uint32_t, 4, Arch > value) noexcept
	Evaluate vpconflictd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	mask_vpconflictd (simd< std::uint32_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > value) noexcept
	Evaluate mask_vpconflictd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	maskz_vpconflictd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > value) noexcept
	Evaluate maskz_vpconflictd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	vplzcntd (simd< std::uint32_t, 4, Arch > value) noexcept
	Evaluate vplzcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	mask_vplzcntd (simd< std::uint32_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > value) noexcept
	Evaluate mask_vplzcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	maskz_vplzcntd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > value) noexcept
	Evaluate maskz_vplzcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	vpconflictq (simd< std::uint64_t, 2, Arch > value) noexcept
	Evaluate vpconflictq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	mask_vpconflictq (simd< std::uint64_t, 2, Arch > source, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > value) noexcept
	Evaluate mask_vpconflictq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	maskz_vpconflictq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > value) noexcept
	Evaluate maskz_vpconflictq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	vplzcntq (simd< std::uint64_t, 2, Arch > value) noexcept
	Evaluate vplzcntq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	mask_vplzcntq (simd< std::uint64_t, 2, Arch > source, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > value) noexcept
	Evaluate mask_vplzcntq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	maskz_vplzcntq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > value) noexcept
	Evaluate maskz_vplzcntq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	vpconflictd (simd< std::uint32_t, 8, Arch > value) noexcept
	Evaluate vpconflictd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	mask_vpconflictd (simd< std::uint32_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > value) noexcept
	Evaluate mask_vpconflictd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	maskz_vpconflictd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > value) noexcept
	Evaluate maskz_vpconflictd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	vplzcntd (simd< std::uint32_t, 8, Arch > value) noexcept
	Evaluate vplzcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	mask_vplzcntd (simd< std::uint32_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > value) noexcept
	Evaluate mask_vplzcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	maskz_vplzcntd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > value) noexcept
	Evaluate maskz_vplzcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	vpconflictq (simd< std::uint64_t, 4, Arch > value) noexcept
	Evaluate vpconflictq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	mask_vpconflictq (simd< std::uint64_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > value) noexcept
	Evaluate mask_vpconflictq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	maskz_vpconflictq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > value) noexcept
	Evaluate maskz_vpconflictq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	vplzcntq (simd< std::uint64_t, 4, Arch > value) noexcept
	Evaluate vplzcntq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	mask_vplzcntq (simd< std::uint64_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > value) noexcept
	Evaluate mask_vplzcntq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	maskz_vplzcntq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > value) noexcept
	Evaluate maskz_vplzcntq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd)) && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	vpconflictd (simd< std::uint32_t, 16, Arch > value) noexcept
	Evaluate vpconflictd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd)) && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	mask_vpconflictd (simd< std::uint32_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > value) noexcept
	Evaluate mask_vpconflictd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd)) && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	maskz_vpconflictd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > value) noexcept
	Evaluate maskz_vpconflictd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd)) && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	vplzcntd (simd< std::uint32_t, 16, Arch > value) noexcept
	Evaluate vplzcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd)) && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	mask_vplzcntd (simd< std::uint32_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > value) noexcept
	Evaluate mask_vplzcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd)) && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	maskz_vplzcntd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > value) noexcept
	Evaluate maskz_vplzcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	vpconflictq (simd< std::uint64_t, 8, Arch > value) noexcept
	Evaluate vpconflictq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	mask_vpconflictq (simd< std::uint64_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > value) noexcept
	Evaluate mask_vpconflictq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	maskz_vpconflictq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > value) noexcept
	Evaluate maskz_vpconflictq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	vplzcntq (simd< std::uint64_t, 8, Arch > value) noexcept
	Evaluate vplzcntq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	mask_vplzcntq (simd< std::uint64_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > value) noexcept
	Evaluate mask_vplzcntq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	maskz_vplzcntq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > value) noexcept
	Evaluate maskz_vplzcntq at compile time when its register storage is available.
template<isa< x86 > Arch, class... Args>
void	vpconflictd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	mask_vpconflictd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	maskz_vpconflictd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	vplzcntd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	mask_vplzcntd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	maskz_vplzcntd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	vpconflictq (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	mask_vpconflictq (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	maskz_vpconflictq (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	vplzcntq (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	mask_vplzcntq (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	maskz_vplzcntq (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, std::size_t N> requires (Arch.has(x86_feature::avxneconvert) && Arch.has(x86_feature::avx) && (N == 4 \|\| N == 8))
constexpr simd< float, N, Arch >	bcstnebf16_ps (bf16 const *source) noexcept
template<isa< x86 > Arch, std::size_t N> requires (!(Arch.has(x86_feature::avxneconvert) && Arch.has(x86_feature::avx)) && (N == 4 \|\| N == 8) && requires { sizeof(simd <float, N, Arch>); })
consteval simd< float, N, Arch >	bcstnebf16_ps (bf16 const *source) noexcept
	Constant-only widening when AVX-NE-CONVERT or AVX is absent.
template<isa< x86 > Arch, std::size_t N> requires (Arch.has(x86_feature::avxneconvert) && Arch.has(x86_feature::avx) && (N == 4 \|\| N == 8))
constexpr simd< float, N, Arch >	bcstnesh_ps (fp16 const *source) noexcept
template<isa< x86 > Arch, std::size_t N> requires (!(Arch.has(x86_feature::avxneconvert) && Arch.has(x86_feature::avx)) && (N == 4 \|\| N == 8) && requires { sizeof(simd <float, N, Arch>); })
consteval simd< float, N, Arch >	bcstnesh_ps (fp16 const *source) noexcept
	Constant-only widening when AVX-NE-CONVERT or AVX is absent.
template<isa< x86 > Arch, std::size_t N> requires (Arch.has(x86_feature::avxneconvert) && Arch.has(x86_feature::avx) && (N == 4 \|\| N == 8))
constexpr simd< float, N, Arch >	cvtneebf16_ps (bf16 const *source) noexcept
template<isa< x86 > Arch, std::size_t N> requires (!(Arch.has(x86_feature::avxneconvert) && Arch.has(x86_feature::avx)) && (N == 4 \|\| N == 8) && requires { sizeof(simd <float, N, Arch>); })
consteval simd< float, N, Arch >	cvtneebf16_ps (bf16 const *source) noexcept
	Constant-only widening when AVX-NE-CONVERT or AVX is absent.
template<isa< x86 > Arch, std::size_t N> requires (Arch.has(x86_feature::avxneconvert) && Arch.has(x86_feature::avx) && (N == 4 \|\| N == 8))
constexpr simd< float, N, Arch >	cvtneeph_ps (fp16 const *source) noexcept
template<isa< x86 > Arch, std::size_t N> requires (!(Arch.has(x86_feature::avxneconvert) && Arch.has(x86_feature::avx)) && (N == 4 \|\| N == 8) && requires { sizeof(simd <float, N, Arch>); })
consteval simd< float, N, Arch >	cvtneeph_ps (fp16 const *source) noexcept
	Constant-only widening when AVX-NE-CONVERT or AVX is absent.
template<isa< x86 > Arch, std::size_t N> requires (Arch.has(x86_feature::avxneconvert) && Arch.has(x86_feature::avx) && (N == 4 \|\| N == 8))
constexpr simd< float, N, Arch >	cvtneobf16_ps (bf16 const *source) noexcept
template<isa< x86 > Arch, std::size_t N> requires (!(Arch.has(x86_feature::avxneconvert) && Arch.has(x86_feature::avx)) && (N == 4 \|\| N == 8) && requires { sizeof(simd <float, N, Arch>); })
consteval simd< float, N, Arch >	cvtneobf16_ps (bf16 const *source) noexcept
	Constant-only widening when AVX-NE-CONVERT or AVX is absent.
template<isa< x86 > Arch, std::size_t N> requires (Arch.has(x86_feature::avxneconvert) && Arch.has(x86_feature::avx) && (N == 4 \|\| N == 8))
constexpr simd< float, N, Arch >	cvtneoph_ps (fp16 const *source) noexcept
template<isa< x86 > Arch, std::size_t N> requires (!(Arch.has(x86_feature::avxneconvert) && Arch.has(x86_feature::avx)) && (N == 4 \|\| N == 8) && requires { sizeof(simd <float, N, Arch>); })
consteval simd< float, N, Arch >	cvtneoph_ps (fp16 const *source) noexcept
	Constant-only widening when AVX-NE-CONVERT or AVX is absent.
template<isa< x86 > Arch, std::size_t N> requires (Arch.has(x86_feature::avxneconvert) && Arch.has(x86_feature::avx) && (N == 4 \|\| N == 8))
constexpr simd< bf16, N, Arch >	cvtneps_bf16 (simd< float, N, Arch > input) noexcept
template<isa< x86 > Arch, std::size_t N> requires (!(Arch.has(x86_feature::avxneconvert) && Arch.has(x86_feature::avx)) && (N == 4 \|\| N == 8) && requires { sizeof(simd <float, N, Arch>); sizeof(simd<bf16, N, Arch>); })
consteval simd< bf16, N, Arch >	cvtneps_bf16 (simd< float, N, Arch > input) noexcept
	Constant-only narrowing when AVX-NE-CONVERT or AVX is absent.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	vpopcntb (simd< std::uint8_t, 16, Arch > value) noexcept
	Count set bits in each 8-bit lane.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	mask_vpopcntb (simd< std::uint8_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Inactive destination lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	maskz_vpopcntb (predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Inactive destination lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	vpopcntw (simd< std::uint16_t, 8, Arch > value) noexcept
	Count set bits in each 16-bit lane.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	mask_vpopcntw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Inactive destination lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	maskz_vpopcntw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Inactive destination lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr predicate< 16, Arch >	vpshufbitqmb (simd< std::uint64_t, 2, Arch > value, simd< std::uint8_t, 16, Arch > control) noexcept
	Select one source bit for each control byte, within the corresponding qword.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr predicate< 16, Arch >	mask_vpshufbitqmb (predicate< 16, Arch > maskmask, simd< std::uint64_t, 2, Arch > value, simd< std::uint8_t, 16, Arch > control) noexcept
	Select source bits for active output positions; inactive predicate bits become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	vpopcntb (simd< std::uint8_t, 32, Arch > value) noexcept
	Count set bits in each 8-bit lane.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	mask_vpopcntb (simd< std::uint8_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Inactive destination lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	maskz_vpopcntb (predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Inactive destination lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	vpopcntw (simd< std::uint16_t, 16, Arch > value) noexcept
	Count set bits in each 16-bit lane.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	mask_vpopcntw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Inactive destination lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	maskz_vpopcntw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Inactive destination lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr predicate< 32, Arch >	vpshufbitqmb (simd< std::uint64_t, 4, Arch > value, simd< std::uint8_t, 32, Arch > control) noexcept
	Select one source bit for each control byte, within the corresponding qword.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr predicate< 32, Arch >	mask_vpshufbitqmb (predicate< 32, Arch > maskmask, simd< std::uint64_t, 4, Arch > value, simd< std::uint8_t, 32, Arch > control) noexcept
	Select source bits for active output positions; inactive predicate bits become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg))
constexpr simd< std::uint8_t, 64, Arch >	vpopcntb (simd< std::uint8_t, 64, Arch > value) noexcept
	Count set bits in each 8-bit lane.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg))
constexpr simd< std::uint8_t, 64, Arch >	mask_vpopcntb (simd< std::uint8_t, 64, Arch > source, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Inactive destination lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg))
constexpr simd< std::uint8_t, 64, Arch >	maskz_vpopcntb (predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Inactive destination lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg))
constexpr simd< std::uint16_t, 32, Arch >	vpopcntw (simd< std::uint16_t, 32, Arch > value) noexcept
	Count set bits in each 16-bit lane.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg))
constexpr simd< std::uint16_t, 32, Arch >	mask_vpopcntw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Inactive destination lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg))
constexpr simd< std::uint16_t, 32, Arch >	maskz_vpopcntw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Inactive destination lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg))
constexpr predicate< 64, Arch >	vpshufbitqmb (simd< std::uint64_t, 8, Arch > value, simd< std::uint8_t, 64, Arch > control) noexcept
	Select one source bit for each control byte, within the corresponding qword.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg))
constexpr predicate< 64, Arch >	mask_vpshufbitqmb (predicate< 64, Arch > maskmask, simd< std::uint64_t, 8, Arch > value, simd< std::uint8_t, 64, Arch > control) noexcept
	Select source bits for active output positions; inactive predicate bits become zero.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	vpopcntb (simd< std::uint8_t, 16, Arch > value) noexcept
	Evaluate vpopcntb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	mask_vpopcntb (simd< std::uint8_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Evaluate mask_vpopcntb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	maskz_vpopcntb (predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Evaluate maskz_vpopcntb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	vpopcntw (simd< std::uint16_t, 8, Arch > value) noexcept
	Evaluate vpopcntw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	mask_vpopcntw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Evaluate mask_vpopcntw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	maskz_vpopcntw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Evaluate maskz_vpopcntw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); sizeof(simd<std::uint8_t, 16, Arch>); sizeof(predicate<16, Arch>); })
consteval predicate< 16, Arch >	vpshufbitqmb (simd< std::uint64_t, 2, Arch > value, simd< std::uint8_t, 16, Arch > control) noexcept
	Evaluate vpshufbitqmb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); sizeof(simd<std::uint8_t, 16, Arch>); sizeof(predicate<16, Arch>); })
consteval predicate< 16, Arch >	mask_vpshufbitqmb (predicate< 16, Arch > maskmask, simd< std::uint64_t, 2, Arch > value, simd< std::uint8_t, 16, Arch > control) noexcept
	Evaluate mask_vpshufbitqmb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	vpopcntb (simd< std::uint8_t, 32, Arch > value) noexcept
	Evaluate vpopcntb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	mask_vpopcntb (simd< std::uint8_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Evaluate mask_vpopcntb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	maskz_vpopcntb (predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Evaluate maskz_vpopcntb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	vpopcntw (simd< std::uint16_t, 16, Arch > value) noexcept
	Evaluate vpopcntw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	mask_vpopcntw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Evaluate mask_vpopcntw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	maskz_vpopcntw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Evaluate maskz_vpopcntw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); sizeof(simd<std::uint8_t, 32, Arch>); sizeof(predicate<32, Arch>); })
consteval predicate< 32, Arch >	vpshufbitqmb (simd< std::uint64_t, 4, Arch > value, simd< std::uint8_t, 32, Arch > control) noexcept
	Evaluate vpshufbitqmb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); sizeof(simd<std::uint8_t, 32, Arch>); sizeof(predicate<32, Arch>); })
consteval predicate< 32, Arch >	mask_vpshufbitqmb (predicate< 32, Arch > maskmask, simd< std::uint64_t, 4, Arch > value, simd< std::uint8_t, 32, Arch > control) noexcept
	Evaluate mask_vpshufbitqmb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	vpopcntb (simd< std::uint8_t, 64, Arch > value) noexcept
	Evaluate vpopcntb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	mask_vpopcntb (simd< std::uint8_t, 64, Arch > source, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Evaluate mask_vpopcntb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	maskz_vpopcntb (predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Evaluate maskz_vpopcntb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg)) && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	vpopcntw (simd< std::uint16_t, 32, Arch > value) noexcept
	Evaluate vpopcntw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg)) && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	mask_vpopcntw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Evaluate mask_vpopcntw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg)) && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	maskz_vpopcntw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Evaluate maskz_vpopcntw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); sizeof(simd<std::uint8_t, 64, Arch>); sizeof(predicate<64, Arch>); })
consteval predicate< 64, Arch >	vpshufbitqmb (simd< std::uint64_t, 8, Arch > value, simd< std::uint8_t, 64, Arch > control) noexcept
	Evaluate vpshufbitqmb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); sizeof(simd<std::uint8_t, 64, Arch>); sizeof(predicate<64, Arch>); })
consteval predicate< 64, Arch >	mask_vpshufbitqmb (predicate< 64, Arch > maskmask, simd< std::uint64_t, 8, Arch > value, simd< std::uint8_t, 64, Arch > control) noexcept
	Evaluate mask_vpshufbitqmb at compile time when its register storage is available.
template<isa< x86 > Arch, class... Args>
void	vpopcntb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	mask_vpopcntb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	maskz_vpopcntb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	vpopcntw (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	mask_vpopcntw (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	maskz_vpopcntw (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	vpshufbitqmb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	mask_vpshufbitqmb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint32_t	andn (std::uint32_t first, std::uint32_t second) noexcept
	ANDN: complement the first operand, then AND with the second.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi1))
consteval std::uint32_t	andn (std::uint32_t first, std::uint32_t second) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint64_t	andn (std::uint64_t first, std::uint64_t second) noexcept
	ANDN, with 64-bit operands.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi1))
consteval std::uint64_t	andn (std::uint64_t first, std::uint64_t second) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint32_t	bextr (std::uint32_t value, std::uint32_t control) noexcept
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi1))
consteval std::uint32_t	bextr (std::uint32_t value, std::uint32_t control) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint64_t	bextr (std::uint64_t value, std::uint32_t control) noexcept
	BEXTR, with a 64-bit value and the same packed control format.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi1))
consteval std::uint64_t	bextr (std::uint64_t value, std::uint32_t control) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint32_t	bextr (std::uint32_t value, unsigned start, unsigned length) noexcept
	BEXTR with separate controls; only the low eight bits of each are used.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi1))
consteval std::uint32_t	bextr (std::uint32_t value, unsigned start, unsigned length) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint64_t	bextr (std::uint64_t value, unsigned start, unsigned length) noexcept
	BEXTR with a 64-bit value and separate low-eight-bit controls.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi1))
consteval std::uint64_t	bextr (std::uint64_t value, unsigned start, unsigned length) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint32_t	blsi (std::uint32_t value) noexcept
	BLSI: retain only the lowest set bit; zero remains zero.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi1))
consteval std::uint32_t	blsi (std::uint32_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint64_t	blsi (std::uint64_t value) noexcept
	BLSI, with a 64-bit operand.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi1))
consteval std::uint64_t	blsi (std::uint64_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint32_t	blsmsk (std::uint32_t value) noexcept
	BLSMSK: set every bit through the lowest set bit; zero produces all ones.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi1))
consteval std::uint32_t	blsmsk (std::uint32_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint64_t	blsmsk (std::uint64_t value) noexcept
	BLSMSK, with a 64-bit operand.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi1))
consteval std::uint64_t	blsmsk (std::uint64_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint32_t	blsr (std::uint32_t value) noexcept
	BLSR: clear the lowest set bit; zero remains zero.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi1))
consteval std::uint32_t	blsr (std::uint32_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint64_t	blsr (std::uint64_t value) noexcept
	BLSR, with a 64-bit operand.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi1))
consteval std::uint64_t	blsr (std::uint64_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint16_t	tzcnt (std::uint16_t value) noexcept
	TZCNT: count low zero bits; zero returns the operand width, including 16-bit operands.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi1))
consteval std::uint16_t	tzcnt (std::uint16_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint32_t	tzcnt (std::uint32_t value) noexcept
	TZCNT, with a 32-bit operand and result; zero returns 32.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi1))
consteval std::uint32_t	tzcnt (std::uint32_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint64_t	tzcnt (std::uint64_t value) noexcept
	TZCNT, with a 64-bit operand and result; zero returns 64.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi1))
consteval std::uint64_t	tzcnt (std::uint64_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	bzhi (std::uint32_t value, unsigned index) noexcept
	Zero bits at and above index's low eight bits; an index at least the width leaves value unchanged.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi2))
consteval std::uint32_t	bzhi (std::uint32_t value, unsigned index) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint64_t	bzhi (std::uint64_t value, unsigned index) noexcept
	BZHI with a 64-bit value and the same low-eight-bit index semantics.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi2))
consteval std::uint64_t	bzhi (std::uint64_t value, unsigned index) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	mulx (std::uint32_t a, std::uint32_t b, std::uint32_t *high) noexcept
	Return the low product and write the high product to a valid output pointer.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi2))
consteval std::uint32_t	mulx (std::uint32_t a, std::uint32_t b, std::uint32_t *high) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint64_t	mulx (std::uint64_t a, std::uint64_t b, std::uint64_t *high) noexcept
	Return the low 64 bits and write the high 64 bits of the unsigned 128-bit product.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi2))
consteval std::uint64_t	mulx (std::uint64_t a, std::uint64_t b, std::uint64_t *high) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	pdep (std::uint32_t value, std::uint32_t maskmask) noexcept
	Parallel bit deposit (PDEP): place the low popcount(mask) bits into mask's set positions, in order.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi2))
consteval std::uint32_t	pdep (std::uint32_t value, std::uint32_t maskmask) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint64_t	pdep (std::uint64_t value, std::uint64_t maskmask) noexcept
	Parallel bit deposit (PDEP), with 64-bit operands.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi2))
consteval std::uint64_t	pdep (std::uint64_t value, std::uint64_t maskmask) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	pext (std::uint32_t value, std::uint32_t maskmask) noexcept
	Parallel bit extract (PEXT): gather mask's selected bits into the low bits, in order.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi2))
consteval std::uint32_t	pext (std::uint32_t value, std::uint32_t maskmask) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint64_t	pext (std::uint64_t value, std::uint64_t maskmask) noexcept
	Parallel bit extract (PEXT), with 64-bit operands.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi2))
consteval std::uint64_t	pext (std::uint64_t value, std::uint64_t maskmask) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	shlx (std::uint32_t value, unsigned count) noexcept
	Logical left shift using the low five bits of count.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi2))
consteval std::uint32_t	shlx (std::uint32_t value, unsigned count) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint64_t	shlx (std::uint64_t value, unsigned count) noexcept
	Logical left shift using the low six bits of count.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi2))
consteval std::uint64_t	shlx (std::uint64_t value, unsigned count) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	shrx (std::uint32_t value, unsigned count) noexcept
	Logical right shift using the low five bits of count.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi2))
consteval std::uint32_t	shrx (std::uint32_t value, unsigned count) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint64_t	shrx (std::uint64_t value, unsigned count) noexcept
	Logical right shift using the low six bits of count.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi2))
consteval std::uint64_t	shrx (std::uint64_t value, unsigned count) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::int32_t	sarx (std::int32_t value, unsigned count) noexcept
	Arithmetic right shift using the low five bits of count, propagating the sign bit.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi2))
consteval std::int32_t	sarx (std::int32_t value, unsigned count) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::int64_t	sarx (std::int64_t value, unsigned count) noexcept
	Arithmetic right shift using the low six bits of count, propagating the sign bit.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi2))
consteval std::int64_t	sarx (std::int64_t value, unsigned count) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<unsigned Imm8, isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2) && Imm8 <= 255)
constexpr std::uint32_t	rorx (std::uint32_t value) noexcept
template<unsigned Imm8, isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2) && Imm8 <= 255)
constexpr std::uint64_t	rorx (std::uint64_t value) noexcept
template<unsigned Imm8, isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi2) && Imm8 <= 255)
consteval std::uint32_t	rorx (std::uint32_t value) noexcept
	Rotate a constant expression when Arch lacks BMI2.
template<unsigned Imm8, isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::bmi2) && Imm8 <= 255)
consteval std::uint64_t	rorx (std::uint64_t value) noexcept
	Rotate a constant expression when Arch lacks BMI2.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::crc32))
constexpr std::uint32_t	crc32c (std::uint32_t accumulator, std::uint8_t value) noexcept
	Update a 32-bit CRC32C accumulator with exactly eight bits.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::crc32))
consteval std::uint32_t	crc32c (std::uint32_t accumulator, std::uint8_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::crc32))
constexpr std::uint32_t	crc32c (std::uint32_t accumulator, std::uint16_t value) noexcept
	Update a 32-bit CRC32C accumulator with exactly sixteen bits.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::crc32))
consteval std::uint32_t	crc32c (std::uint32_t accumulator, std::uint16_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::crc32))
constexpr std::uint32_t	crc32c (std::uint32_t accumulator, std::uint32_t value) noexcept
	Update a 32-bit CRC32C accumulator with exactly thirty-two bits.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::crc32))
consteval std::uint32_t	crc32c (std::uint32_t accumulator, std::uint32_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::f16c) && Imm8 <= 255)
constexpr simd< fp16, 4, Arch >	cvtps_ph (simd< float, 4, Arch > a) noexcept
	Convert 4 binary32 lanes to 4 binary16 lanes.
template<isa< x86 > Arch, unsigned Imm8> requires (requires { sizeof(simd<float,4,Arch>); sizeof(simd<fp16,4,Arch>); } && !Arch.has(x86_feature::f16c) && Imm8 <= 255)
consteval simd< fp16, 4, Arch >	cvtps_ph (simd< float, 4, Arch > a) noexcept
	Constant-evaluation-only form for an ISA without F16C.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::f16c) && Imm8 <= 255)
constexpr simd< fp16, 8, Arch >	cvtps_ph (simd< float, 8, Arch > a) noexcept
	Convert 8 binary32 lanes to 8 binary16 lanes.
template<isa< x86 > Arch, unsigned Imm8> requires (requires { sizeof(simd<float,8,Arch>); sizeof(simd<fp16,8,Arch>); } && !Arch.has(x86_feature::f16c) && Imm8 <= 255)
consteval simd< fp16, 8, Arch >	cvtps_ph (simd< float, 8, Arch > a) noexcept
	Constant-evaluation-only form for an ISA without F16C.
template<isa< x86 > Arch, unsigned Lanes> requires (Arch.has(x86_feature::f16c) && Lanes == 4)
constexpr simd< float, 4, Arch >	cvtph_ps (simd< fp16, 4, Arch > a) noexcept
	Widen 4 binary16 lanes to 4 binary32 lanes.
template<isa< x86 > Arch, unsigned Lanes> requires (requires { sizeof(simd<float,4,Arch>); sizeof(simd<fp16,4,Arch>); } && !Arch.has(x86_feature::f16c) && Lanes == 4)
consteval simd< float, 4, Arch >	cvtph_ps (simd< fp16, 4, Arch > a) noexcept
	Constant-evaluation-only form for an ISA without F16C.
template<isa< x86 > Arch, unsigned Lanes> requires (Arch.has(x86_feature::f16c) && Lanes == 8)
constexpr simd< float, 8, Arch >	cvtph_ps (simd< fp16, 8, Arch > a) noexcept
	Widen 8 binary16 lanes to 8 binary32 lanes.
template<isa< x86 > Arch, unsigned Lanes> requires (requires { sizeof(simd<float,8,Arch>); sizeof(simd<fp16,8,Arch>); } && !Arch.has(x86_feature::f16c) && Lanes == 8)
consteval simd< float, 8, Arch >	cvtph_ps (simd< fp16, 8, Arch > a) noexcept
	Constant-evaluation-only form for an ISA without F16C.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::f16c) && Imm8 <= 255)
constexpr std::uint16_t	cvtss_sh (float a) noexcept
	Convert one binary32 value to binary16 representation bits.
template<isa< x86 > Arch, unsigned Imm8> requires (!Arch.has(x86_feature::f16c) && Imm8 <= 255)
consteval std::uint16_t	cvtss_sh (float a) noexcept
	Constant-evaluation-only form for an ISA without F16C.
template<unsigned Imm8, isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::f16c) && Imm8 <= 255)
constexpr std::uint16_t	cvtss_sh (float a) noexcept
template<unsigned Imm8, isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::f16c) && Imm8 <= 255)
consteval std::uint16_t	cvtss_sh (float a) noexcept
	Constant-evaluation-only form for an ISA without F16C.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::f16c))
constexpr float	cvtsh_ss (std::uint16_t a) noexcept
	Widen one binary16 representation to binary32.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::f16c))
consteval float	cvtsh_ss (std::uint16_t a) noexcept
	Constant-evaluation-only form for an ISA without F16C.
template<isa< x86 > Arch, unsigned Imm8, class V>
void	cvtps_ph (V)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, unsigned Lanes, class V>
void	cvtph_ps (V)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
cpuid_t	cpuid (std::int32_t eax, std::int32_t ecx) noexcept
x86_capabilities	observe_x86_capabilities () noexcept
	Capture CPUID and, only with XSAVE and OSXSAVE, XCR0. No ISA profile required.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni))
constexpr simd< std::uint8_t, 16, Arch >	gf2p8mulb (simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Multiply corresponding bytes in GF(2^8).
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Imm8 <= 255)
constexpr simd< std::uint8_t, 16, Arch >	gf2p8affineqb (simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept
	Apply the binary matrix in each 64-bit lane and XOR Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Imm8 <= 255)
constexpr simd< std::uint8_t, 16, Arch >	gf2p8affineinvqb (simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept
	Invert each field byte, apply its lane's binary matrix, and XOR Imm8.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	gf2p8mulb_mask (simd< std::uint8_t, 16, Arch > src, predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Merge inactive bytes from src after gf2p8mulb.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	gf2p8mulb_maskz (predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Zero inactive bytes after gf2p8mulb.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint8_t, 16, Arch >	gf2p8affineqb_mask (simd< std::uint8_t, 16, Arch > src, predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept
	Merge inactive bytes from src after gf2p8affineqb.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint8_t, 16, Arch >	gf2p8affineqb_maskz (predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept
	Zero inactive bytes after gf2p8affineqb.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint8_t, 16, Arch >	gf2p8affineinvqb_mask (simd< std::uint8_t, 16, Arch > src, predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept
	Merge inactive bytes from src after gf2p8affineinvqb.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint8_t, 16, Arch >	gf2p8affineinvqb_maskz (predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept
	Zero inactive bytes after gf2p8affineinvqb.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx))
constexpr simd< std::uint8_t, 32, Arch >	gf2p8mulb (simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Multiply corresponding bytes in GF(2^8).
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx) && Imm8 <= 255)
constexpr simd< std::uint8_t, 32, Arch >	gf2p8affineqb (simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept
	Apply the binary matrix in each 64-bit lane and XOR Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx) && Imm8 <= 255)
constexpr simd< std::uint8_t, 32, Arch >	gf2p8affineinvqb (simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept
	Invert each field byte, apply its lane's binary matrix, and XOR Imm8.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	gf2p8mulb_mask (simd< std::uint8_t, 32, Arch > src, predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Merge inactive bytes from src after gf2p8mulb.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	gf2p8mulb_maskz (predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Zero inactive bytes after gf2p8mulb.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint8_t, 32, Arch >	gf2p8affineqb_mask (simd< std::uint8_t, 32, Arch > src, predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept
	Merge inactive bytes from src after gf2p8affineqb.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint8_t, 32, Arch >	gf2p8affineqb_maskz (predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept
	Zero inactive bytes after gf2p8affineqb.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint8_t, 32, Arch >	gf2p8affineinvqb_mask (simd< std::uint8_t, 32, Arch > src, predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept
	Merge inactive bytes from src after gf2p8affineinvqb.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint8_t, 32, Arch >	gf2p8affineinvqb_maskz (predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept
	Zero inactive bytes after gf2p8affineinvqb.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f))
constexpr simd< std::uint8_t, 64, Arch >	gf2p8mulb (simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept
	Multiply corresponding bytes in GF(2^8).
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Imm8 <= 255)
constexpr simd< std::uint8_t, 64, Arch >	gf2p8affineqb (simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept
	Apply the binary matrix in each 64-bit lane and XOR Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Imm8 <= 255)
constexpr simd< std::uint8_t, 64, Arch >	gf2p8affineinvqb (simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept
	Invert each field byte, apply its lane's binary matrix, and XOR Imm8.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw))
constexpr simd< std::uint8_t, 64, Arch >	gf2p8mulb_mask (simd< std::uint8_t, 64, Arch > src, predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept
	Merge inactive bytes from src after gf2p8mulb.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw))
constexpr simd< std::uint8_t, 64, Arch >	gf2p8mulb_maskz (predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept
	Zero inactive bytes after gf2p8mulb.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Imm8 <= 255)
constexpr simd< std::uint8_t, 64, Arch >	gf2p8affineqb_mask (simd< std::uint8_t, 64, Arch > src, predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept
	Merge inactive bytes from src after gf2p8affineqb.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Imm8 <= 255)
constexpr simd< std::uint8_t, 64, Arch >	gf2p8affineqb_maskz (predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept
	Zero inactive bytes after gf2p8affineqb.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Imm8 <= 255)
constexpr simd< std::uint8_t, 64, Arch >	gf2p8affineinvqb_mask (simd< std::uint8_t, 64, Arch > src, predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept
	Merge inactive bytes from src after gf2p8affineinvqb.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Imm8 <= 255)
constexpr simd< std::uint8_t, 64, Arch >	gf2p8affineinvqb_maskz (predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept
	Zero inactive bytes after gf2p8affineinvqb.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni))) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	gf2p8mulb (simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate gf2p8mulb at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd <std::uint64_t, 2, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	gf2p8affineqb (simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept
	Evaluate gf2p8affineqb at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd <std::uint64_t, 2, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	gf2p8affineinvqb (simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept
	Evaluate gf2p8affineinvqb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	gf2p8mulb_mask (simd< std::uint8_t, 16, Arch > src, predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate gf2p8mulb_mask at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	gf2p8mulb_maskz (predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate gf2p8mulb_maskz at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	gf2p8affineqb_mask (simd< std::uint8_t, 16, Arch > src, predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept
	Evaluate gf2p8affineqb_mask at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	gf2p8affineqb_maskz (predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept
	Evaluate gf2p8affineqb_maskz at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	gf2p8affineinvqb_mask (simd< std::uint8_t, 16, Arch > src, predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept
	Evaluate gf2p8affineinvqb_mask at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	gf2p8affineinvqb_maskz (predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept
	Evaluate gf2p8affineinvqb_maskz at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx))) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	gf2p8mulb (simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Evaluate gf2p8mulb at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	gf2p8affineqb (simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept
	Evaluate gf2p8affineqb at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	gf2p8affineinvqb (simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept
	Evaluate gf2p8affineinvqb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	gf2p8mulb_mask (simd< std::uint8_t, 32, Arch > src, predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Evaluate gf2p8mulb_mask at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	gf2p8mulb_maskz (predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Evaluate gf2p8mulb_maskz at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	gf2p8affineqb_mask (simd< std::uint8_t, 32, Arch > src, predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept
	Evaluate gf2p8affineqb_mask at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	gf2p8affineqb_maskz (predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept
	Evaluate gf2p8affineqb_maskz at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	gf2p8affineinvqb_mask (simd< std::uint8_t, 32, Arch > src, predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept
	Evaluate gf2p8affineinvqb_mask at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	gf2p8affineinvqb_maskz (predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept
	Evaluate gf2p8affineinvqb_maskz at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f))) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	gf2p8mulb (simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept
	Evaluate gf2p8mulb at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f))) && Imm8 <= 255 && requires { sizeof(simd <std::uint8_t, 64, Arch>); sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	gf2p8affineqb (simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept
	Evaluate gf2p8affineqb at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f))) && Imm8 <= 255 && requires { sizeof(simd <std::uint8_t, 64, Arch>); sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	gf2p8affineinvqb (simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept
	Evaluate gf2p8affineinvqb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw))) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	gf2p8mulb_mask (simd< std::uint8_t, 64, Arch > src, predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept
	Evaluate gf2p8mulb_mask at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw))) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	gf2p8mulb_maskz (predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept
	Evaluate gf2p8mulb_maskz at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 64, Arch>); sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	gf2p8affineqb_mask (simd< std::uint8_t, 64, Arch > src, predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept
	Evaluate gf2p8affineqb_mask at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 64, Arch>); sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	gf2p8affineqb_maskz (predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept
	Evaluate gf2p8affineqb_maskz at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 64, Arch>); sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	gf2p8affineinvqb_mask (simd< std::uint8_t, 64, Arch > src, predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept
	Evaluate gf2p8affineinvqb_mask at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 64, Arch>); sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	gf2p8affineinvqb_maskz (predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept
	Evaluate gf2p8affineinvqb_maskz at compile time when its register storage is available.
template<isa< x86 > Arch, class... Args>
void	gf2p8mulb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	gf2p8affineqb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	gf2p8affineinvqb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	gf2p8mulb_mask (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	gf2p8mulb_maskz (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	gf2p8affineqb_mask (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	gf2p8affineqb_maskz (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	gf2p8affineinvqb_mask (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	gf2p8affineinvqb_maskz (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxifma) && Arch.has(x86_feature::avx))
constexpr simd< std::uint64_t, 2, Arch >	madd52lo (simd< std::uint64_t, 2, Arch > accumulator, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Accumulate low 52-bit products in 2 lanes; unmasked.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avxifma) && Arch.has(x86_feature::avx)) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	madd52lo (simd< std::uint64_t, 2, Arch > accumulator, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Accumulate low 52-bit products in 2 lanes; unmasked.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxifma) && Arch.has(x86_feature::avx)) \|\| (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	madd52lo (simd< std::uint64_t, 2, Arch > accumulator, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxifma) && Arch.has(x86_feature::avx))
constexpr simd< std::uint64_t, 4, Arch >	madd52lo (simd< std::uint64_t, 4, Arch > accumulator, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Accumulate low 52-bit products in 4 lanes; unmasked.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avxifma) && Arch.has(x86_feature::avx)) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	madd52lo (simd< std::uint64_t, 4, Arch > accumulator, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Accumulate low 52-bit products in 4 lanes; unmasked.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxifma) && Arch.has(x86_feature::avx)) \|\| (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	madd52lo (simd< std::uint64_t, 4, Arch > accumulator, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma))
constexpr simd< std::uint64_t, 8, Arch >	madd52lo (simd< std::uint64_t, 8, Arch > accumulator, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Accumulate low 52-bit products in 8 lanes; unmasked.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	madd52lo (simd< std::uint64_t, 8, Arch > accumulator, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch, class... Args>
void	madd52lo (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector or mask shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	mask_madd52lo (simd< std::uint64_t, 2, Arch > accumulator, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Accumulate low 52-bit products in 2 lanes; inactive lanes retain the accumulator.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	mask_madd52lo (simd< std::uint64_t, 2, Arch > accumulator, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	mask_madd52lo (simd< std::uint64_t, 4, Arch > accumulator, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Accumulate low 52-bit products in 4 lanes; inactive lanes retain the accumulator.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	mask_madd52lo (simd< std::uint64_t, 4, Arch > accumulator, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma))
constexpr simd< std::uint64_t, 8, Arch >	mask_madd52lo (simd< std::uint64_t, 8, Arch > accumulator, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Accumulate low 52-bit products in 8 lanes; inactive lanes retain the accumulator.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	mask_madd52lo (simd< std::uint64_t, 8, Arch > accumulator, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch, class... Args>
void	mask_madd52lo (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector or mask shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	maskz_madd52lo (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > accumulator, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Accumulate low 52-bit products in 2 lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	maskz_madd52lo (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > accumulator, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	maskz_madd52lo (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > accumulator, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Accumulate low 52-bit products in 4 lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	maskz_madd52lo (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > accumulator, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma))
constexpr simd< std::uint64_t, 8, Arch >	maskz_madd52lo (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > accumulator, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Accumulate low 52-bit products in 8 lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	maskz_madd52lo (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > accumulator, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch, class... Args>
void	maskz_madd52lo (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector or mask shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxifma) && Arch.has(x86_feature::avx))
constexpr simd< std::uint64_t, 2, Arch >	madd52hi (simd< std::uint64_t, 2, Arch > accumulator, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Accumulate high 52-bit products in 2 lanes; unmasked.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avxifma) && Arch.has(x86_feature::avx)) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	madd52hi (simd< std::uint64_t, 2, Arch > accumulator, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Accumulate high 52-bit products in 2 lanes; unmasked.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxifma) && Arch.has(x86_feature::avx)) \|\| (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	madd52hi (simd< std::uint64_t, 2, Arch > accumulator, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxifma) && Arch.has(x86_feature::avx))
constexpr simd< std::uint64_t, 4, Arch >	madd52hi (simd< std::uint64_t, 4, Arch > accumulator, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Accumulate high 52-bit products in 4 lanes; unmasked.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avxifma) && Arch.has(x86_feature::avx)) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	madd52hi (simd< std::uint64_t, 4, Arch > accumulator, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Accumulate high 52-bit products in 4 lanes; unmasked.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxifma) && Arch.has(x86_feature::avx)) \|\| (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	madd52hi (simd< std::uint64_t, 4, Arch > accumulator, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma))
constexpr simd< std::uint64_t, 8, Arch >	madd52hi (simd< std::uint64_t, 8, Arch > accumulator, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Accumulate high 52-bit products in 8 lanes; unmasked.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	madd52hi (simd< std::uint64_t, 8, Arch > accumulator, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch, class... Args>
void	madd52hi (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector or mask shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	mask_madd52hi (simd< std::uint64_t, 2, Arch > accumulator, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Accumulate high 52-bit products in 2 lanes; inactive lanes retain the accumulator.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	mask_madd52hi (simd< std::uint64_t, 2, Arch > accumulator, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	mask_madd52hi (simd< std::uint64_t, 4, Arch > accumulator, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Accumulate high 52-bit products in 4 lanes; inactive lanes retain the accumulator.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	mask_madd52hi (simd< std::uint64_t, 4, Arch > accumulator, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma))
constexpr simd< std::uint64_t, 8, Arch >	mask_madd52hi (simd< std::uint64_t, 8, Arch > accumulator, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Accumulate high 52-bit products in 8 lanes; inactive lanes retain the accumulator.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	mask_madd52hi (simd< std::uint64_t, 8, Arch > accumulator, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch, class... Args>
void	mask_madd52hi (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector or mask shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	maskz_madd52hi (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > accumulator, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Accumulate high 52-bit products in 2 lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	maskz_madd52hi (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > accumulator, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	maskz_madd52hi (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > accumulator, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Accumulate high 52-bit products in 4 lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	maskz_madd52hi (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > accumulator, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma))
constexpr simd< std::uint64_t, 8, Arch >	maskz_madd52hi (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > accumulator, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Accumulate high 52-bit products in 8 lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	maskz_madd52hi (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > accumulator, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Constant evaluation without the instruction features.
template<isa< x86 > Arch, class... Args>
void	maskz_madd52hi (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector or mask shapes.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::lzcnt))
constexpr std::uint16_t	lzcnt (std::uint16_t value) noexcept
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::lzcnt))
consteval std::uint16_t	lzcnt (std::uint16_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::lzcnt))
constexpr std::uint32_t	lzcnt (std::uint32_t value) noexcept
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::lzcnt))
consteval std::uint32_t	lzcnt (std::uint32_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::lzcnt))
constexpr std::uint64_t	lzcnt (std::uint64_t value) noexcept
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::lzcnt))
consteval std::uint64_t	lzcnt (std::uint64_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<int Scale, std::size_t N, isa< x86 > Arch> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4)
constexpr simd< float, 4, Arch >	vgatherdps (float const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather all addressable lanes; N specifies the result lane count.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< float, 4, Arch >	mask_vgatherdps (simd< float, 4, Arch > source, simd< std::int32_t, 4, Arch > maskmask, float const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather lanes whose full vector mask has its sign bit set; retain source otherwise.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< float, 4, Arch >	mask_vgatherdps (simd< float, 4, Arch > source, predicate< 4, Arch > maskmask, float const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr void	mask_vscatterdps (float *base, predicate< 4, Arch > maskmask, simd< std::int32_t, 4, Arch > indices, simd< float, 4, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, std::size_t N, isa< x86 > Arch> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 8)
constexpr simd< float, 8, Arch >	vgatherdps (float const *base, simd< std::int32_t, 8, Arch > indices) noexcept
	Gather all addressable lanes; N specifies the result lane count.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< float, 8, Arch >	mask_vgatherdps (simd< float, 8, Arch > source, simd< std::int32_t, 8, Arch > maskmask, float const *base, simd< std::int32_t, 8, Arch > indices) noexcept
	Gather lanes whose full vector mask has its sign bit set; retain source otherwise.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< float, 8, Arch >	mask_vgatherdps (simd< float, 8, Arch > source, predicate< 8, Arch > maskmask, float const *base, simd< std::int32_t, 8, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr void	mask_vscatterdps (float *base, predicate< 8, Arch > maskmask, simd< std::int32_t, 8, Arch > indices, simd< float, 8, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< float, 16, Arch >	mask_vgatherdps (simd< float, 16, Arch > source, predicate< 16, Arch > maskmask, float const *base, simd< std::int32_t, 16, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr void	mask_vscatterdps (float *base, predicate< 16, Arch > maskmask, simd< std::int32_t, 16, Arch > indices, simd< float, 16, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, std::size_t N, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4 && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr simd< T, 4, Arch >	vpgatherdd (T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather all addressable lanes; N specifies the result lane count.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr simd< T, 4, Arch >	mask_vpgatherdd (simd< T, 4, Arch > source, simd< std::int32_t, 4, Arch > maskmask, T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather lanes whose full vector mask has its sign bit set; retain source otherwise.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr simd< T, 4, Arch >	mask_vpgatherdd (simd< T, 4, Arch > source, predicate< 4, Arch > maskmask, T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr void	mask_vpscatterdd (T *base, predicate< 4, Arch > maskmask, simd< std::int32_t, 4, Arch > indices, simd< T, 4, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, std::size_t N, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 8 && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr simd< T, 8, Arch >	vpgatherdd (T const *base, simd< std::int32_t, 8, Arch > indices) noexcept
	Gather all addressable lanes; N specifies the result lane count.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr simd< T, 8, Arch >	mask_vpgatherdd (simd< T, 8, Arch > source, simd< std::int32_t, 8, Arch > maskmask, T const *base, simd< std::int32_t, 8, Arch > indices) noexcept
	Gather lanes whose full vector mask has its sign bit set; retain source otherwise.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr simd< T, 8, Arch >	mask_vpgatherdd (simd< T, 8, Arch > source, predicate< 8, Arch > maskmask, T const *base, simd< std::int32_t, 8, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr void	mask_vpscatterdd (T *base, predicate< 8, Arch > maskmask, simd< std::int32_t, 8, Arch > indices, simd< T, 8, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr simd< T, 16, Arch >	mask_vpgatherdd (simd< T, 16, Arch > source, predicate< 16, Arch > maskmask, T const *base, simd< std::int32_t, 16, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr void	mask_vpscatterdd (T *base, predicate< 16, Arch > maskmask, simd< std::int32_t, 16, Arch > indices, simd< T, 16, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, std::size_t N, isa< x86 > Arch> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 2)
constexpr simd< double, 2, Arch >	vgatherdpd (double const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather all addressable lanes; N specifies the result lane count.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< double, 2, Arch >	mask_vgatherdpd (simd< double, 2, Arch > source, simd< std::int64_t, 2, Arch > maskmask, double const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather lanes whose full vector mask has its sign bit set; retain source otherwise.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< double, 2, Arch >	mask_vgatherdpd (simd< double, 2, Arch > source, predicate< 2, Arch > maskmask, double const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr void	mask_vscatterdpd (double *base, predicate< 2, Arch > maskmask, simd< std::int32_t, 4, Arch > indices, simd< double, 2, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, std::size_t N, isa< x86 > Arch> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4)
constexpr simd< double, 4, Arch >	vgatherdpd (double const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather all addressable lanes; N specifies the result lane count.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< double, 4, Arch >	mask_vgatherdpd (simd< double, 4, Arch > source, simd< std::int64_t, 4, Arch > maskmask, double const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather lanes whose full vector mask has its sign bit set; retain source otherwise.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< double, 4, Arch >	mask_vgatherdpd (simd< double, 4, Arch > source, predicate< 4, Arch > maskmask, double const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr void	mask_vscatterdpd (double *base, predicate< 4, Arch > maskmask, simd< std::int32_t, 4, Arch > indices, simd< double, 4, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< double, 8, Arch >	mask_vgatherdpd (simd< double, 8, Arch > source, predicate< 8, Arch > maskmask, double const *base, simd< std::int32_t, 8, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr void	mask_vscatterdpd (double *base, predicate< 8, Arch > maskmask, simd< std::int32_t, 8, Arch > indices, simd< double, 8, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, std::size_t N, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 2 && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr simd< T, 2, Arch >	vpgatherdq (T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather all addressable lanes; N specifies the result lane count.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr simd< T, 2, Arch >	mask_vpgatherdq (simd< T, 2, Arch > source, simd< std::int64_t, 2, Arch > maskmask, T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather lanes whose full vector mask has its sign bit set; retain source otherwise.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr simd< T, 2, Arch >	mask_vpgatherdq (simd< T, 2, Arch > source, predicate< 2, Arch > maskmask, T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr void	mask_vpscatterdq (T *base, predicate< 2, Arch > maskmask, simd< std::int32_t, 4, Arch > indices, simd< T, 2, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, std::size_t N, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4 && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr simd< T, 4, Arch >	vpgatherdq (T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather all addressable lanes; N specifies the result lane count.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr simd< T, 4, Arch >	mask_vpgatherdq (simd< T, 4, Arch > source, simd< std::int64_t, 4, Arch > maskmask, T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather lanes whose full vector mask has its sign bit set; retain source otherwise.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr simd< T, 4, Arch >	mask_vpgatherdq (simd< T, 4, Arch > source, predicate< 4, Arch > maskmask, T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr void	mask_vpscatterdq (T *base, predicate< 4, Arch > maskmask, simd< std::int32_t, 4, Arch > indices, simd< T, 4, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr simd< T, 8, Arch >	mask_vpgatherdq (simd< T, 8, Arch > source, predicate< 8, Arch > maskmask, T const *base, simd< std::int32_t, 8, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr void	mask_vpscatterdq (T *base, predicate< 8, Arch > maskmask, simd< std::int32_t, 8, Arch > indices, simd< T, 8, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, std::size_t N, isa< x86 > Arch> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4)
constexpr simd< float, 4, Arch >	vgatherqps (float const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Gather all addressable lanes; N specifies the result lane count.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< float, 4, Arch >	mask_vgatherqps (simd< float, 4, Arch > source, simd< std::int32_t, 4, Arch > maskmask, float const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Gather lanes whose full vector mask has its sign bit set; retain source otherwise.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< float, 4, Arch >	mask_vgatherqps (simd< float, 4, Arch > source, predicate< 4, Arch > maskmask, float const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr void	mask_vscatterqps (float *base, predicate< 4, Arch > maskmask, simd< std::int64_t, 2, Arch > indices, simd< float, 4, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, std::size_t N, isa< x86 > Arch> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4)
constexpr simd< float, 4, Arch >	vgatherqps (float const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Gather all addressable lanes; N specifies the result lane count.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< float, 4, Arch >	mask_vgatherqps (simd< float, 4, Arch > source, simd< std::int32_t, 4, Arch > maskmask, float const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Gather lanes whose full vector mask has its sign bit set; retain source otherwise.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< float, 4, Arch >	mask_vgatherqps (simd< float, 4, Arch > source, predicate< 4, Arch > maskmask, float const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr void	mask_vscatterqps (float *base, predicate< 4, Arch > maskmask, simd< std::int64_t, 4, Arch > indices, simd< float, 4, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< float, 8, Arch >	mask_vgatherqps (simd< float, 8, Arch > source, predicate< 8, Arch > maskmask, float const *base, simd< std::int64_t, 8, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr void	mask_vscatterqps (float *base, predicate< 8, Arch > maskmask, simd< std::int64_t, 8, Arch > indices, simd< float, 8, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, std::size_t N, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4 && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr simd< T, 4, Arch >	vpgatherqd (T const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Gather all addressable lanes; N specifies the result lane count.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr simd< T, 4, Arch >	mask_vpgatherqd (simd< T, 4, Arch > source, simd< std::int32_t, 4, Arch > maskmask, T const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Gather lanes whose full vector mask has its sign bit set; retain source otherwise.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr simd< T, 4, Arch >	mask_vpgatherqd (simd< T, 4, Arch > source, predicate< 4, Arch > maskmask, T const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr void	mask_vpscatterqd (T *base, predicate< 4, Arch > maskmask, simd< std::int64_t, 2, Arch > indices, simd< T, 4, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, std::size_t N, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4 && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr simd< T, 4, Arch >	vpgatherqd (T const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Gather all addressable lanes; N specifies the result lane count.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr simd< T, 4, Arch >	mask_vpgatherqd (simd< T, 4, Arch > source, simd< std::int32_t, 4, Arch > maskmask, T const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Gather lanes whose full vector mask has its sign bit set; retain source otherwise.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr simd< T, 4, Arch >	mask_vpgatherqd (simd< T, 4, Arch > source, predicate< 4, Arch > maskmask, T const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr void	mask_vpscatterqd (T *base, predicate< 4, Arch > maskmask, simd< std::int64_t, 4, Arch > indices, simd< T, 4, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr simd< T, 8, Arch >	mask_vpgatherqd (simd< T, 8, Arch > source, predicate< 8, Arch > maskmask, T const *base, simd< std::int64_t, 8, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>))
constexpr void	mask_vpscatterqd (T *base, predicate< 8, Arch > maskmask, simd< std::int64_t, 8, Arch > indices, simd< T, 8, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, std::size_t N, isa< x86 > Arch> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 2)
constexpr simd< double, 2, Arch >	vgatherqpd (double const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Gather all addressable lanes; N specifies the result lane count.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< double, 2, Arch >	mask_vgatherqpd (simd< double, 2, Arch > source, simd< std::int64_t, 2, Arch > maskmask, double const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Gather lanes whose full vector mask has its sign bit set; retain source otherwise.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< double, 2, Arch >	mask_vgatherqpd (simd< double, 2, Arch > source, predicate< 2, Arch > maskmask, double const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr void	mask_vscatterqpd (double *base, predicate< 2, Arch > maskmask, simd< std::int64_t, 2, Arch > indices, simd< double, 2, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, std::size_t N, isa< x86 > Arch> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4)
constexpr simd< double, 4, Arch >	vgatherqpd (double const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Gather all addressable lanes; N specifies the result lane count.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< double, 4, Arch >	mask_vgatherqpd (simd< double, 4, Arch > source, simd< std::int64_t, 4, Arch > maskmask, double const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Gather lanes whose full vector mask has its sign bit set; retain source otherwise.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< double, 4, Arch >	mask_vgatherqpd (simd< double, 4, Arch > source, predicate< 4, Arch > maskmask, double const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr void	mask_vscatterqpd (double *base, predicate< 4, Arch > maskmask, simd< std::int64_t, 4, Arch > indices, simd< double, 4, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr simd< double, 8, Arch >	mask_vgatherqpd (simd< double, 8, Arch > source, predicate< 8, Arch > maskmask, double const *base, simd< std::int64_t, 8, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8))
constexpr void	mask_vscatterqpd (double *base, predicate< 8, Arch > maskmask, simd< std::int64_t, 8, Arch > indices, simd< double, 8, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, std::size_t N, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 2 && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr simd< T, 2, Arch >	vpgatherqq (T const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Gather all addressable lanes; N specifies the result lane count.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr simd< T, 2, Arch >	mask_vpgatherqq (simd< T, 2, Arch > source, simd< std::int64_t, 2, Arch > maskmask, T const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Gather lanes whose full vector mask has its sign bit set; retain source otherwise.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr simd< T, 2, Arch >	mask_vpgatherqq (simd< T, 2, Arch > source, predicate< 2, Arch > maskmask, T const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr void	mask_vpscatterqq (T *base, predicate< 2, Arch > maskmask, simd< std::int64_t, 2, Arch > indices, simd< T, 2, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, std::size_t N, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4 && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr simd< T, 4, Arch >	vpgatherqq (T const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Gather all addressable lanes; N specifies the result lane count.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx2) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr simd< T, 4, Arch >	mask_vpgatherqq (simd< T, 4, Arch > source, simd< std::int64_t, 4, Arch > maskmask, T const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Gather lanes whose full vector mask has its sign bit set; retain source otherwise.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr simd< T, 4, Arch >	mask_vpgatherqq (simd< T, 4, Arch > source, predicate< 4, Arch > maskmask, T const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr void	mask_vpscatterqq (T *base, predicate< 4, Arch > maskmask, simd< std::int64_t, 4, Arch > indices, simd< T, 4, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr simd< T, 8, Arch >	mask_vpgatherqq (simd< T, 8, Arch > source, predicate< 8, Arch > maskmask, T const *base, simd< std::int64_t, 8, Arch > indices) noexcept
	Gather predicate-selected lanes; retain source in inactive addressable lanes.
template<int Scale, isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>))
constexpr void	mask_vpscatterqq (T *base, predicate< 8, Arch > maskmask, simd< std::int64_t, 8, Arch > indices, simd< T, 8, Arch > value) noexcept
	Store predicate-selected lanes; inactive addresses are not accessed.
template<int Scale, std::size_t N, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4 && requires { sizeof(simd <float, 4, Arch>); sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< float, 4, Arch >	vgatherdps (float const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd <float, 4, Arch>); sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< float, 4, Arch >	mask_vgatherdps (simd< float, 4, Arch > source, simd< std::int32_t, 4, Arch > maskmask, float const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd<float, 4, Arch>); sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< float, 4, Arch >	mask_vgatherdps (simd< float, 4, Arch > source, predicate< 4, Arch > maskmask, float const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd<float, 4, Arch>); sizeof(simd<std::int32_t, 4, Arch>); })
consteval void	mask_vscatterdps (float *base, predicate< 4, Arch > maskmask, simd< std::int32_t, 4, Arch > indices, simd< float, 4, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, std::size_t N, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 8 && requires { sizeof(simd <float, 8, Arch>); sizeof(simd<std::int32_t, 8, Arch>); })
consteval simd< float, 8, Arch >	vgatherdps (float const *base, simd< std::int32_t, 8, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd <float, 8, Arch>); sizeof(simd<std::int32_t, 8, Arch>); })
consteval simd< float, 8, Arch >	mask_vgatherdps (simd< float, 8, Arch > source, simd< std::int32_t, 8, Arch > maskmask, float const *base, simd< std::int32_t, 8, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd<float, 8, Arch>); sizeof(simd<std::int32_t, 8, Arch>); })
consteval simd< float, 8, Arch >	mask_vgatherdps (simd< float, 8, Arch > source, predicate< 8, Arch > maskmask, float const *base, simd< std::int32_t, 8, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd<float, 8, Arch>); sizeof(simd<std::int32_t, 8, Arch>); })
consteval void	mask_vscatterdps (float *base, predicate< 8, Arch > maskmask, simd< std::int32_t, 8, Arch > indices, simd< float, 8, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd <float, 16, Arch>); sizeof(simd<std::int32_t, 16, Arch>); })
consteval simd< float, 16, Arch >	mask_vgatherdps (simd< float, 16, Arch > source, predicate< 16, Arch > maskmask, float const *base, simd< std::int32_t, 16, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd <float, 16, Arch>); sizeof(simd<std::int32_t, 16, Arch>); })
consteval void	mask_vscatterdps (float *base, predicate< 16, Arch > maskmask, simd< std::int32_t, 16, Arch > indices, simd< float, 16, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, std::size_t N, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4 && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 4, Arch>); sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< T, 4, Arch >	vpgatherdd (T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 4, Arch>); sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< T, 4, Arch >	mask_vpgatherdd (simd< T, 4, Arch > source, simd< std::int32_t, 4, Arch > maskmask, T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 4, Arch> ); sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< T, 4, Arch >	mask_vpgatherdd (simd< T, 4, Arch > source, predicate< 4, Arch > maskmask, T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 4, Arch> ); sizeof(simd<std::int32_t, 4, Arch>); })
consteval void	mask_vpscatterdd (T *base, predicate< 4, Arch > maskmask, simd< std::int32_t, 4, Arch > indices, simd< T, 4, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, std::size_t N, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 8 && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 8, Arch>); sizeof(simd<std::int32_t, 8, Arch>); })
consteval simd< T, 8, Arch >	vpgatherdd (T const *base, simd< std::int32_t, 8, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 8, Arch>); sizeof(simd<std::int32_t, 8, Arch>); })
consteval simd< T, 8, Arch >	mask_vpgatherdd (simd< T, 8, Arch > source, simd< std::int32_t, 8, Arch > maskmask, T const *base, simd< std::int32_t, 8, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 8, Arch> ); sizeof(simd<std::int32_t, 8, Arch>); })
consteval simd< T, 8, Arch >	mask_vpgatherdd (simd< T, 8, Arch > source, predicate< 8, Arch > maskmask, T const *base, simd< std::int32_t, 8, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 8, Arch> ); sizeof(simd<std::int32_t, 8, Arch>); })
consteval void	mask_vpscatterdd (T *base, predicate< 8, Arch > maskmask, simd< std::int32_t, 8, Arch > indices, simd< T, 8, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 16, Arch>); sizeof(simd<std::int32_t, 16, Arch>); })
consteval simd< T, 16, Arch >	mask_vpgatherdd (simd< T, 16, Arch > source, predicate< 16, Arch > maskmask, T const *base, simd< std::int32_t, 16, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 16, Arch>); sizeof(simd<std::int32_t, 16, Arch>); })
consteval void	mask_vpscatterdd (T *base, predicate< 16, Arch > maskmask, simd< std::int32_t, 16, Arch > indices, simd< T, 16, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, std::size_t N, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 2 && requires { sizeof(simd <double, 2, Arch>); sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< double, 2, Arch >	vgatherdpd (double const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd <double, 2, Arch>); sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int64_t, 2, Arch>); })
consteval simd< double, 2, Arch >	mask_vgatherdpd (simd< double, 2, Arch > source, simd< std::int64_t, 2, Arch > maskmask, double const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd<double, 2, Arch>); sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< double, 2, Arch >	mask_vgatherdpd (simd< double, 2, Arch > source, predicate< 2, Arch > maskmask, double const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd<double, 2, Arch>); sizeof(simd<std::int32_t, 4, Arch>); })
consteval void	mask_vscatterdpd (double *base, predicate< 2, Arch > maskmask, simd< std::int32_t, 4, Arch > indices, simd< double, 2, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, std::size_t N, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4 && requires { sizeof(simd <double, 4, Arch>); sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< double, 4, Arch >	vgatherdpd (double const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd <double, 4, Arch>); sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int64_t, 4, Arch>); })
consteval simd< double, 4, Arch >	mask_vgatherdpd (simd< double, 4, Arch > source, simd< std::int64_t, 4, Arch > maskmask, double const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd<double, 4, Arch>); sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< double, 4, Arch >	mask_vgatherdpd (simd< double, 4, Arch > source, predicate< 4, Arch > maskmask, double const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd<double, 4, Arch>); sizeof(simd<std::int32_t, 4, Arch>); })
consteval void	mask_vscatterdpd (double *base, predicate< 4, Arch > maskmask, simd< std::int32_t, 4, Arch > indices, simd< double, 4, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd <double, 8, Arch>); sizeof(simd<std::int32_t, 8, Arch>); })
consteval simd< double, 8, Arch >	mask_vgatherdpd (simd< double, 8, Arch > source, predicate< 8, Arch > maskmask, double const *base, simd< std::int32_t, 8, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd <double, 8, Arch>); sizeof(simd<std::int32_t, 8, Arch>); })
consteval void	mask_vscatterdpd (double *base, predicate< 8, Arch > maskmask, simd< std::int32_t, 8, Arch > indices, simd< double, 8, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, std::size_t N, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 2 && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 2, Arch>); sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< T, 2, Arch >	vpgatherdq (T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 2, Arch>); sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int64_t, 2, Arch>); })
consteval simd< T, 2, Arch >	mask_vpgatherdq (simd< T, 2, Arch > source, simd< std::int64_t, 2, Arch > maskmask, T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 2, Arch> ); sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< T, 2, Arch >	mask_vpgatherdq (simd< T, 2, Arch > source, predicate< 2, Arch > maskmask, T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 2, Arch> ); sizeof(simd<std::int32_t, 4, Arch>); })
consteval void	mask_vpscatterdq (T *base, predicate< 2, Arch > maskmask, simd< std::int32_t, 4, Arch > indices, simd< T, 2, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, std::size_t N, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4 && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 4, Arch>); sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< T, 4, Arch >	vpgatherdq (T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 4, Arch>); sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int64_t, 4, Arch>); })
consteval simd< T, 4, Arch >	mask_vpgatherdq (simd< T, 4, Arch > source, simd< std::int64_t, 4, Arch > maskmask, T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 4, Arch> ); sizeof(simd<std::int32_t, 4, Arch>); })
consteval simd< T, 4, Arch >	mask_vpgatherdq (simd< T, 4, Arch > source, predicate< 4, Arch > maskmask, T const *base, simd< std::int32_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 4, Arch> ); sizeof(simd<std::int32_t, 4, Arch>); })
consteval void	mask_vpscatterdq (T *base, predicate< 4, Arch > maskmask, simd< std::int32_t, 4, Arch > indices, simd< T, 4, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 8, Arch>); sizeof(simd<std::int32_t, 8, Arch>); })
consteval simd< T, 8, Arch >	mask_vpgatherdq (simd< T, 8, Arch > source, predicate< 8, Arch > maskmask, T const *base, simd< std::int32_t, 8, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 8, Arch>); sizeof(simd<std::int32_t, 8, Arch>); })
consteval void	mask_vpscatterdq (T *base, predicate< 8, Arch > maskmask, simd< std::int32_t, 8, Arch > indices, simd< T, 8, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, std::size_t N, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4 && requires { sizeof(simd <float, 4, Arch>); sizeof(simd<std::int64_t, 2, Arch>); })
consteval simd< float, 4, Arch >	vgatherqps (float const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd <float, 4, Arch>); sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int64_t, 2, Arch>); })
consteval simd< float, 4, Arch >	mask_vgatherqps (simd< float, 4, Arch > source, simd< std::int32_t, 4, Arch > maskmask, float const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd<float, 4, Arch>); sizeof(simd<std::int64_t, 2, Arch>); })
consteval simd< float, 4, Arch >	mask_vgatherqps (simd< float, 4, Arch > source, predicate< 4, Arch > maskmask, float const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd<float, 4, Arch>); sizeof(simd<std::int64_t, 2, Arch>); })
consteval void	mask_vscatterqps (float *base, predicate< 4, Arch > maskmask, simd< std::int64_t, 2, Arch > indices, simd< float, 4, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, std::size_t N, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4 && requires { sizeof(simd <float, 4, Arch>); sizeof(simd<std::int64_t, 4, Arch>); })
consteval simd< float, 4, Arch >	vgatherqps (float const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd <float, 4, Arch>); sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int64_t, 4, Arch>); })
consteval simd< float, 4, Arch >	mask_vgatherqps (simd< float, 4, Arch > source, simd< std::int32_t, 4, Arch > maskmask, float const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd<float, 4, Arch>); sizeof(simd<std::int64_t, 4, Arch>); })
consteval simd< float, 4, Arch >	mask_vgatherqps (simd< float, 4, Arch > source, predicate< 4, Arch > maskmask, float const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd<float, 4, Arch>); sizeof(simd<std::int64_t, 4, Arch>); })
consteval void	mask_vscatterqps (float *base, predicate< 4, Arch > maskmask, simd< std::int64_t, 4, Arch > indices, simd< float, 4, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd <float, 8, Arch>); sizeof(simd<std::int64_t, 8, Arch>); })
consteval simd< float, 8, Arch >	mask_vgatherqps (simd< float, 8, Arch > source, predicate< 8, Arch > maskmask, float const *base, simd< std::int64_t, 8, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd <float, 8, Arch>); sizeof(simd<std::int64_t, 8, Arch>); })
consteval void	mask_vscatterqps (float *base, predicate< 8, Arch > maskmask, simd< std::int64_t, 8, Arch > indices, simd< float, 8, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, std::size_t N, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4 && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 4, Arch>); sizeof(simd<std::int64_t, 2, Arch>); })
consteval simd< T, 4, Arch >	vpgatherqd (T const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 4, Arch>); sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int64_t, 2, Arch>); })
consteval simd< T, 4, Arch >	mask_vpgatherqd (simd< T, 4, Arch > source, simd< std::int32_t, 4, Arch > maskmask, T const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 4, Arch> ); sizeof(simd<std::int64_t, 2, Arch>); })
consteval simd< T, 4, Arch >	mask_vpgatherqd (simd< T, 4, Arch > source, predicate< 4, Arch > maskmask, T const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 4, Arch> ); sizeof(simd<std::int64_t, 2, Arch>); })
consteval void	mask_vpscatterqd (T *base, predicate< 4, Arch > maskmask, simd< std::int64_t, 2, Arch > indices, simd< T, 4, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, std::size_t N, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4 && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 4, Arch>); sizeof(simd<std::int64_t, 4, Arch>); })
consteval simd< T, 4, Arch >	vpgatherqd (T const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 4, Arch>); sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int64_t, 4, Arch>); })
consteval simd< T, 4, Arch >	mask_vpgatherqd (simd< T, 4, Arch > source, simd< std::int32_t, 4, Arch > maskmask, T const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 4, Arch> ); sizeof(simd<std::int64_t, 4, Arch>); })
consteval simd< T, 4, Arch >	mask_vpgatherqd (simd< T, 4, Arch > source, predicate< 4, Arch > maskmask, T const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 4, Arch> ); sizeof(simd<std::int64_t, 4, Arch>); })
consteval void	mask_vpscatterqd (T *base, predicate< 4, Arch > maskmask, simd< std::int64_t, 4, Arch > indices, simd< T, 4, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 8, Arch>); sizeof(simd<std::int64_t, 8, Arch>); })
consteval simd< T, 8, Arch >	mask_vpgatherqd (simd< T, 8, Arch > source, predicate< 8, Arch > maskmask, T const *base, simd< std::int64_t, 8, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int32_t> \|\| std::same_as<T, std::uint32_t>) && requires { sizeof(simd<T, 8, Arch>); sizeof(simd<std::int64_t, 8, Arch>); })
consteval void	mask_vpscatterqd (T *base, predicate< 8, Arch > maskmask, simd< std::int64_t, 8, Arch > indices, simd< T, 8, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, std::size_t N, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 2 && requires { sizeof(simd <double, 2, Arch>); sizeof(simd<std::int64_t, 2, Arch>); })
consteval simd< double, 2, Arch >	vgatherqpd (double const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd <double, 2, Arch>); sizeof(simd<std::int64_t, 2, Arch>); })
consteval simd< double, 2, Arch >	mask_vgatherqpd (simd< double, 2, Arch > source, simd< std::int64_t, 2, Arch > maskmask, double const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd<double, 2, Arch>); sizeof(simd<std::int64_t, 2, Arch>); })
consteval simd< double, 2, Arch >	mask_vgatherqpd (simd< double, 2, Arch > source, predicate< 2, Arch > maskmask, double const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd<double, 2, Arch>); sizeof(simd<std::int64_t, 2, Arch>); })
consteval void	mask_vscatterqpd (double *base, predicate< 2, Arch > maskmask, simd< std::int64_t, 2, Arch > indices, simd< double, 2, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, std::size_t N, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4 && requires { sizeof(simd <double, 4, Arch>); sizeof(simd<std::int64_t, 4, Arch>); })
consteval simd< double, 4, Arch >	vgatherqpd (double const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd <double, 4, Arch>); sizeof(simd<std::int64_t, 4, Arch>); })
consteval simd< double, 4, Arch >	mask_vgatherqpd (simd< double, 4, Arch > source, simd< std::int64_t, 4, Arch > maskmask, double const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd<double, 4, Arch>); sizeof(simd<std::int64_t, 4, Arch>); })
consteval simd< double, 4, Arch >	mask_vgatherqpd (simd< double, 4, Arch > source, predicate< 4, Arch > maskmask, double const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd<double, 4, Arch>); sizeof(simd<std::int64_t, 4, Arch>); })
consteval void	mask_vscatterqpd (double *base, predicate< 4, Arch > maskmask, simd< std::int64_t, 4, Arch > indices, simd< double, 4, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd <double, 8, Arch>); sizeof(simd<std::int64_t, 8, Arch>); })
consteval simd< double, 8, Arch >	mask_vgatherqpd (simd< double, 8, Arch > source, predicate< 8, Arch > maskmask, double const *base, simd< std::int64_t, 8, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && requires { sizeof(simd <double, 8, Arch>); sizeof(simd<std::int64_t, 8, Arch>); })
consteval void	mask_vscatterqpd (double *base, predicate< 8, Arch > maskmask, simd< std::int64_t, 8, Arch > indices, simd< double, 8, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, std::size_t N, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 2 && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 2, Arch>); sizeof(simd<std::int64_t, 2, Arch>); })
consteval simd< T, 2, Arch >	vpgatherqq (T const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 2, Arch>); sizeof(simd<std::int64_t, 2, Arch>); })
consteval simd< T, 2, Arch >	mask_vpgatherqq (simd< T, 2, Arch > source, simd< std::int64_t, 2, Arch > maskmask, T const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 2, Arch> ); sizeof(simd<std::int64_t, 2, Arch>); })
consteval simd< T, 2, Arch >	mask_vpgatherqq (simd< T, 2, Arch > source, predicate< 2, Arch > maskmask, T const *base, simd< std::int64_t, 2, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 2, Arch> ); sizeof(simd<std::int64_t, 2, Arch>); })
consteval void	mask_vpscatterqq (T *base, predicate< 2, Arch > maskmask, simd< std::int64_t, 2, Arch > indices, simd< T, 2, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, std::size_t N, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && N == 4 && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 4, Arch>); sizeof(simd<std::int64_t, 4, Arch>); })
consteval simd< T, 4, Arch >	vpgatherqq (T const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx2)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 4, Arch>); sizeof(simd<std::int64_t, 4, Arch>); })
consteval simd< T, 4, Arch >	mask_vpgatherqq (simd< T, 4, Arch > source, simd< std::int64_t, 4, Arch > maskmask, T const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 4, Arch> ); sizeof(simd<std::int64_t, 4, Arch>); })
consteval simd< T, 4, Arch >	mask_vpgatherqq (simd< T, 4, Arch > source, predicate< 4, Arch > maskmask, T const *base, simd< std::int64_t, 4, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vl)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 4, Arch> ); sizeof(simd<std::int64_t, 4, Arch>); })
consteval void	mask_vpscatterqq (T *base, predicate< 4, Arch > maskmask, simd< std::int64_t, 4, Arch > indices, simd< T, 4, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 8, Arch>); sizeof(simd<std::int64_t, 8, Arch>); })
consteval simd< T, 8, Arch >	mask_vpgatherqq (simd< T, 8, Arch > source, predicate< 8, Arch > maskmask, T const *base, simd< std::int64_t, 8, Arch > indices) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<int Scale, isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f)) && (Scale == 1 \|\| Scale == 2 \|\| Scale == 4 \|\| Scale == 8) && (std::same_as<T, std::int64_t> \|\| std::same_as<T, std::uint64_t>) && requires { sizeof(simd<T, 8, Arch>); sizeof(simd<std::int64_t, 8, Arch>); })
consteval void	mask_vpscatterqq (T *base, predicate< 8, Arch > maskmask, simd< std::int64_t, 8, Arch > indices, simd< T, 8, Arch > value) noexcept
	Evaluate this hardware shape only at compile time when its storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::pclmul) && Imm8 <= 255)
constexpr simd< std::uint64_t, 2, Arch >	pclmulqdq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::pclmul))) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	pclmulqdq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Evaluate pclmulqdq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	pclmulqdq (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::popcnt))
constexpr std::uint16_t	popcnt (std::uint16_t value) noexcept
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::popcnt))
consteval std::uint16_t	popcnt (std::uint16_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::popcnt))
constexpr std::uint32_t	popcnt (std::uint32_t value) noexcept
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::popcnt))
consteval std::uint32_t	popcnt (std::uint32_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::popcnt))
constexpr std::uint64_t	popcnt (std::uint64_t value) noexcept
template<isa< x86 > Arch = NATIVE_BASELINE> requires (!Arch.has(x86_feature::popcnt))
consteval std::uint64_t	popcnt (std::uint64_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch, unsigned Selector> requires (Arch.has(x86_feature::sha) && Selector < 4)
constexpr simd< std::uint32_t, 4, Arch >	sha1rnds4 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Four SHA-1 rounds; Selector in [0,3] selects the function and constant.
template<isa< x86 > Arch, unsigned Selector> requires (!Arch.has(x86_feature::sha) && Selector < 4 && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sha1rnds4 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Evaluate constant operands without SHA.
template<isa< x86 > Arch, unsigned Selector, class... Args>
void	sha1rnds4 (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::sha))
constexpr simd< std::uint32_t, 4, Arch >	sha1nexte (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Add the next E value, derived from a, to the high dword of b.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::sha) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sha1nexte (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Evaluate constant operands without SHA.
template<isa< x86 > Arch, class... Args>
void	sha1nexte (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::sha))
constexpr simd< std::uint32_t, 4, Arch >	sha1msg1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	First SHA-1 message-schedule step.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::sha) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sha1msg1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Evaluate constant operands without SHA.
template<isa< x86 > Arch, class... Args>
void	sha1msg1 (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::sha))
constexpr simd< std::uint32_t, 4, Arch >	sha1msg2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Final SHA-1 message-schedule step.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::sha) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sha1msg2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Evaluate constant operands without SHA.
template<isa< x86 > Arch, class... Args>
void	sha1msg2 (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::sha))
constexpr simd< std::uint32_t, 4, Arch >	sha256rnds2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Two SHA-256 rounds: a is CDGH, b is ABEF, c contains two message-plus-constant words.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::sha) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sha256rnds2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Evaluate constant operands without SHA.
template<isa< x86 > Arch, class... Args>
void	sha256rnds2 (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::sha))
constexpr simd< std::uint32_t, 4, Arch >	sha256msg1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	First SHA-256 message-schedule step.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::sha) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sha256msg1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Evaluate constant operands without SHA.
template<isa< x86 > Arch, class... Args>
void	sha256msg1 (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::sha))
constexpr simd< std::uint32_t, 4, Arch >	sha256msg2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Final SHA-256 message-schedule step.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::sha) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sha256msg2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Evaluate constant operands without SHA.
template<isa< x86 > Arch, class... Args>
void	sha256msg2 (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::sha512) && Arch.has(x86_feature::avx))
constexpr simd< std::uint64_t, 4, Arch >	sha512msg1 (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	First SHA-512 schedule step; only the low lane of b is used.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::sha512) && Arch.has(x86_feature::avx)) && requires { sizeof(simd<std::uint64_t, 2, Arch> ); sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	sha512msg1 (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Evaluate constant operands without SHA512.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::sha512) && Arch.has(x86_feature::avx))
constexpr simd< std::uint64_t, 4, Arch >	sha512msg2 (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Final SHA-512 schedule step with recurrence through the low output lanes.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::sha512) && Arch.has(x86_feature::avx)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	sha512msg2 (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Evaluate constant operands without SHA512.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::sha512) && Arch.has(x86_feature::avx))
constexpr simd< std::uint64_t, 4, Arch >	sha512rnds2 (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 2, Arch > c) noexcept
	Two SHA-512 rounds: a is CDGH, b is ABEF, c contains two message-plus-constant words.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::sha512) && Arch.has(x86_feature::avx)) && requires { sizeof(simd<std::uint64_t, 2, Arch> ); sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	sha512rnds2 (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 2, Arch > c) noexcept
	Evaluate constant operands without SHA512.
template<isa< x86 > Arch, class... Args>
void	sha512msg1 (Args...)=delete
	Reject raw registers, mixed requirements and unsupported shapes.
template<isa< x86 > Arch, class... Args>
void	sha512msg2 (Args...)=delete
	Reject raw registers, mixed requirements and unsupported shapes.
template<isa< x86 > Arch, class... Args>
void	sha512rnds2 (Args...)=delete
	Reject raw registers, mixed requirements and unsupported shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::sm3) && Arch.has(x86_feature::avx))
constexpr simd< std::uint32_t, 4, Arch >	sm3msg1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	First SM3 schedule step.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::sm3) && Arch.has(x86_feature::avx)) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sm3msg1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Evaluate constant operands without SM3.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::sm3) && Arch.has(x86_feature::avx))
constexpr simd< std::uint32_t, 4, Arch >	sm3msg2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Final SM3 schedule step.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::sm3) && Arch.has(x86_feature::avx)) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sm3msg2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Evaluate constant operands without SM3.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::sm3) && Arch.has(x86_feature::avx) && Imm8 <= 255)
constexpr simd< std::uint32_t, 4, Arch >	sm3rnds2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Two SM3 rounds; Imm8 is masked with 0x3e. a holds unrotated CDGH and b holds ABEF.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::sm3) && Arch.has(x86_feature::avx)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sm3rnds2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
	Evaluate constant operands without SM3.
template<isa< x86 > Arch, class... Args>
void	sm3msg1 (Args...)=delete
	Reject raw registers, mixed requirements and unsupported shapes.
template<isa< x86 > Arch, class... Args>
void	sm3msg2 (Args...)=delete
	Reject raw registers, mixed requirements and unsupported shapes.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	sm3rnds2 (Args...)=delete
	Reject raw registers, mixed requirements and unsupported shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::sm4) && Arch.has(x86_feature::avx))
constexpr simd< std::uint32_t, 4, Arch >	sm4rnds4 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Four SM4 data rounds independently within each 128-bit block; a is state, b is keys.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::sm4) && Arch.has(x86_feature::avx)) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sm4rnds4 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Evaluate constant operands without SM4.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::sm4) && Arch.has(x86_feature::avx))
constexpr simd< std::uint32_t, 4, Arch >	sm4key4 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Four SM4 key-schedule rounds independently within each 128-bit block; a is state, b is constants.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::sm4) && Arch.has(x86_feature::avx)) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	sm4key4 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Evaluate constant operands without SM4.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::sm4) && Arch.has(x86_feature::avx))
constexpr simd< std::uint32_t, 8, Arch >	sm4rnds4 (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Four SM4 data rounds independently within each 128-bit block; a is state, b is keys.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::sm4) && Arch.has(x86_feature::avx)) && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	sm4rnds4 (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Evaluate constant operands without SM4.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::sm4) && Arch.has(x86_feature::avx))
constexpr simd< std::uint32_t, 8, Arch >	sm4key4 (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Four SM4 key-schedule rounds independently within each 128-bit block; a is state, b is constants.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::sm4) && Arch.has(x86_feature::avx)) && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	sm4key4 (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Evaluate constant operands without SM4.
template<isa< x86 > Arch, class... Args>
void	sm4rnds4 (Args...)=delete
	Reject raw registers, mixed requirements and unsupported shapes.
template<isa< x86 > Arch, class... Args>
void	sm4key4 (Args...)=delete
	Reject raw registers, mixed requirements and unsupported shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::aes) && Arch.has(x86_feature::avx))
constexpr simd< std::uint8_t, 16, Arch >	vaesenc (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > key) noexcept
	One AES encryption round.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::aes) && Arch.has(x86_feature::avx)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	vaesenc (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > key) noexcept
	Evaluate constant operands without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx))
constexpr simd< std::uint8_t, 32, Arch >	vaesenc (simd< std::uint8_t, 32, Arch > state, simd< std::uint8_t, 32, Arch > key) noexcept
	Two independent AES encryption rounds.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	vaesenc (simd< std::uint8_t, 32, Arch > state, simd< std::uint8_t, 32, Arch > key) noexcept
	Evaluate constant operands without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx512f))
constexpr simd< std::uint8_t, 64, Arch >	vaesenc (simd< std::uint8_t, 64, Arch > state, simd< std::uint8_t, 64, Arch > key) noexcept
	Four independent AES encryption rounds.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx512f)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	vaesenc (simd< std::uint8_t, 64, Arch > state, simd< std::uint8_t, 64, Arch > key) noexcept
	Evaluate constant operands without the instruction features.
template<isa< x86 > Arch, class... Args>
void	vaesenc (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::aes) && Arch.has(x86_feature::avx))
constexpr simd< std::uint8_t, 16, Arch >	vaesenclast (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > key) noexcept
	One final AES encryption round.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::aes) && Arch.has(x86_feature::avx)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	vaesenclast (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > key) noexcept
	Evaluate constant operands without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx))
constexpr simd< std::uint8_t, 32, Arch >	vaesenclast (simd< std::uint8_t, 32, Arch > state, simd< std::uint8_t, 32, Arch > key) noexcept
	Two independent final AES encryption rounds.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	vaesenclast (simd< std::uint8_t, 32, Arch > state, simd< std::uint8_t, 32, Arch > key) noexcept
	Evaluate constant operands without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx512f))
constexpr simd< std::uint8_t, 64, Arch >	vaesenclast (simd< std::uint8_t, 64, Arch > state, simd< std::uint8_t, 64, Arch > key) noexcept
	Four independent final AES encryption rounds.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx512f)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	vaesenclast (simd< std::uint8_t, 64, Arch > state, simd< std::uint8_t, 64, Arch > key) noexcept
	Evaluate constant operands without the instruction features.
template<isa< x86 > Arch, class... Args>
void	vaesenclast (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::aes) && Arch.has(x86_feature::avx))
constexpr simd< std::uint8_t, 16, Arch >	vaesdec (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > key) noexcept
	One AES decryption round.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::aes) && Arch.has(x86_feature::avx)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	vaesdec (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > key) noexcept
	Evaluate constant operands without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx))
constexpr simd< std::uint8_t, 32, Arch >	vaesdec (simd< std::uint8_t, 32, Arch > state, simd< std::uint8_t, 32, Arch > key) noexcept
	Two independent AES decryption rounds.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	vaesdec (simd< std::uint8_t, 32, Arch > state, simd< std::uint8_t, 32, Arch > key) noexcept
	Evaluate constant operands without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx512f))
constexpr simd< std::uint8_t, 64, Arch >	vaesdec (simd< std::uint8_t, 64, Arch > state, simd< std::uint8_t, 64, Arch > key) noexcept
	Four independent AES decryption rounds.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx512f)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	vaesdec (simd< std::uint8_t, 64, Arch > state, simd< std::uint8_t, 64, Arch > key) noexcept
	Evaluate constant operands without the instruction features.
template<isa< x86 > Arch, class... Args>
void	vaesdec (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::aes) && Arch.has(x86_feature::avx))
constexpr simd< std::uint8_t, 16, Arch >	vaesdeclast (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > key) noexcept
	One final AES decryption round.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::aes) && Arch.has(x86_feature::avx)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	vaesdeclast (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > key) noexcept
	Evaluate constant operands without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx))
constexpr simd< std::uint8_t, 32, Arch >	vaesdeclast (simd< std::uint8_t, 32, Arch > state, simd< std::uint8_t, 32, Arch > key) noexcept
	Two independent final AES decryption rounds.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	vaesdeclast (simd< std::uint8_t, 32, Arch > state, simd< std::uint8_t, 32, Arch > key) noexcept
	Evaluate constant operands without the instruction features.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx512f))
constexpr simd< std::uint8_t, 64, Arch >	vaesdeclast (simd< std::uint8_t, 64, Arch > state, simd< std::uint8_t, 64, Arch > key) noexcept
	Four independent final AES decryption rounds.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx512f)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	vaesdeclast (simd< std::uint8_t, 64, Arch > state, simd< std::uint8_t, 64, Arch > key) noexcept
	Evaluate constant operands without the instruction features.
template<isa< x86 > Arch, class... Args>
void	vaesdeclast (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	vpermb (simd< std::uint8_t, 16, Arch > indices, simd< std::uint8_t, 16, Arch > value) noexcept
	Permute bytes across the whole vector using the low index bits.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	mask_vpermb (simd< std::uint8_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > indices, simd< std::uint8_t, 16, Arch > value) noexcept
	Inactive destination bytes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	maskz_vpermb (predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > indices, simd< std::uint8_t, 16, Arch > value) noexcept
	Inactive destination bytes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	vpermt2b (simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > indices, simd< std::uint8_t, 16, Arch > b) noexcept
	Permute bytes from two tables; the table index spans both complete vectors.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	mask_vpermt2b (simd< std::uint8_t, 16, Arch > a, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > indices, simd< std::uint8_t, 16, Arch > b) noexcept
	Inactive destination bytes retain the first table a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	maskz_vpermt2b (predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > indices, simd< std::uint8_t, 16, Arch > b) noexcept
	Inactive destination bytes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	vpermi2b (simd< std::uint8_t, 16, Arch > indices, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Permute bytes from two tables with the index vector as the tied destination.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	mask_vpermi2b (simd< std::uint8_t, 16, Arch > indices, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Inactive destination bytes retain the index vector.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	maskz_vpermi2b (predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > indices, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Inactive destination bytes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	vpmultishiftqb (simd< std::uint8_t, 16, Arch > control, simd< std::uint64_t, 2, Arch > value) noexcept
	Select eight wrapping bits per control byte from its corresponding source qword.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	mask_vpmultishiftqb (simd< std::uint8_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > control, simd< std::uint64_t, 2, Arch > value) noexcept
	Inactive destination bytes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	maskz_vpmultishiftqb (predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > control, simd< std::uint64_t, 2, Arch > value) noexcept
	Inactive destination bytes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	vpermb (simd< std::uint8_t, 32, Arch > indices, simd< std::uint8_t, 32, Arch > value) noexcept
	Permute bytes across the whole vector using the low index bits.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	mask_vpermb (simd< std::uint8_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > indices, simd< std::uint8_t, 32, Arch > value) noexcept
	Inactive destination bytes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	maskz_vpermb (predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > indices, simd< std::uint8_t, 32, Arch > value) noexcept
	Inactive destination bytes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	vpermt2b (simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > indices, simd< std::uint8_t, 32, Arch > b) noexcept
	Permute bytes from two tables; the table index spans both complete vectors.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	mask_vpermt2b (simd< std::uint8_t, 32, Arch > a, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > indices, simd< std::uint8_t, 32, Arch > b) noexcept
	Inactive destination bytes retain the first table a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	maskz_vpermt2b (predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > indices, simd< std::uint8_t, 32, Arch > b) noexcept
	Inactive destination bytes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	vpermi2b (simd< std::uint8_t, 32, Arch > indices, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Permute bytes from two tables with the index vector as the tied destination.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	mask_vpermi2b (simd< std::uint8_t, 32, Arch > indices, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Inactive destination bytes retain the index vector.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	maskz_vpermi2b (predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > indices, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Inactive destination bytes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	vpmultishiftqb (simd< std::uint8_t, 32, Arch > control, simd< std::uint64_t, 4, Arch > value) noexcept
	Select eight wrapping bits per control byte from its corresponding source qword.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	mask_vpmultishiftqb (simd< std::uint8_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > control, simd< std::uint64_t, 4, Arch > value) noexcept
	Inactive destination bytes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	maskz_vpmultishiftqb (predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > control, simd< std::uint64_t, 4, Arch > value) noexcept
	Inactive destination bytes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi))
constexpr simd< std::uint8_t, 64, Arch >	vpermb (simd< std::uint8_t, 64, Arch > indices, simd< std::uint8_t, 64, Arch > value) noexcept
	Permute bytes across the whole vector using the low index bits.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi))
constexpr simd< std::uint8_t, 64, Arch >	mask_vpermb (simd< std::uint8_t, 64, Arch > source, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > indices, simd< std::uint8_t, 64, Arch > value) noexcept
	Inactive destination bytes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi))
constexpr simd< std::uint8_t, 64, Arch >	maskz_vpermb (predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > indices, simd< std::uint8_t, 64, Arch > value) noexcept
	Inactive destination bytes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi))
constexpr simd< std::uint8_t, 64, Arch >	vpermt2b (simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > indices, simd< std::uint8_t, 64, Arch > b) noexcept
	Permute bytes from two tables; the table index spans both complete vectors.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi))
constexpr simd< std::uint8_t, 64, Arch >	mask_vpermt2b (simd< std::uint8_t, 64, Arch > a, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > indices, simd< std::uint8_t, 64, Arch > b) noexcept
	Inactive destination bytes retain the first table a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi))
constexpr simd< std::uint8_t, 64, Arch >	maskz_vpermt2b (predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > indices, simd< std::uint8_t, 64, Arch > b) noexcept
	Inactive destination bytes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi))
constexpr simd< std::uint8_t, 64, Arch >	vpermi2b (simd< std::uint8_t, 64, Arch > indices, simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept
	Permute bytes from two tables with the index vector as the tied destination.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi))
constexpr simd< std::uint8_t, 64, Arch >	mask_vpermi2b (simd< std::uint8_t, 64, Arch > indices, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept
	Inactive destination bytes retain the index vector.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi))
constexpr simd< std::uint8_t, 64, Arch >	maskz_vpermi2b (predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > indices, simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept
	Inactive destination bytes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi))
constexpr simd< std::uint8_t, 64, Arch >	vpmultishiftqb (simd< std::uint8_t, 64, Arch > control, simd< std::uint64_t, 8, Arch > value) noexcept
	Select eight wrapping bits per control byte from its corresponding source qword.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi))
constexpr simd< std::uint8_t, 64, Arch >	mask_vpmultishiftqb (simd< std::uint8_t, 64, Arch > source, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > control, simd< std::uint64_t, 8, Arch > value) noexcept
	Inactive destination bytes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi))
constexpr simd< std::uint8_t, 64, Arch >	maskz_vpmultishiftqb (predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > control, simd< std::uint64_t, 8, Arch > value) noexcept
	Inactive destination bytes become zero.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	vpermb (simd< std::uint8_t, 16, Arch > indices, simd< std::uint8_t, 16, Arch > value) noexcept
	Evaluate vpermb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	mask_vpermb (simd< std::uint8_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > indices, simd< std::uint8_t, 16, Arch > value) noexcept
	Evaluate mask_vpermb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	maskz_vpermb (predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > indices, simd< std::uint8_t, 16, Arch > value) noexcept
	Evaluate maskz_vpermb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	vpermt2b (simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > indices, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate vpermt2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	mask_vpermt2b (simd< std::uint8_t, 16, Arch > a, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > indices, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate mask_vpermt2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	maskz_vpermt2b (predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > indices, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate maskz_vpermt2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	vpermi2b (simd< std::uint8_t, 16, Arch > indices, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate vpermi2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	mask_vpermi2b (simd< std::uint8_t, 16, Arch > indices, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate mask_vpermi2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	maskz_vpermi2b (predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > indices, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate maskz_vpermi2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	vpmultishiftqb (simd< std::uint8_t, 16, Arch > control, simd< std::uint64_t, 2, Arch > value) noexcept
	Evaluate vpmultishiftqb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	mask_vpmultishiftqb (simd< std::uint8_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > control, simd< std::uint64_t, 2, Arch > value) noexcept
	Evaluate mask_vpmultishiftqb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	maskz_vpmultishiftqb (predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > control, simd< std::uint64_t, 2, Arch > value) noexcept
	Evaluate maskz_vpmultishiftqb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	vpermb (simd< std::uint8_t, 32, Arch > indices, simd< std::uint8_t, 32, Arch > value) noexcept
	Evaluate vpermb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	mask_vpermb (simd< std::uint8_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > indices, simd< std::uint8_t, 32, Arch > value) noexcept
	Evaluate mask_vpermb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	maskz_vpermb (predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > indices, simd< std::uint8_t, 32, Arch > value) noexcept
	Evaluate maskz_vpermb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	vpermt2b (simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > indices, simd< std::uint8_t, 32, Arch > b) noexcept
	Evaluate vpermt2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	mask_vpermt2b (simd< std::uint8_t, 32, Arch > a, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > indices, simd< std::uint8_t, 32, Arch > b) noexcept
	Evaluate mask_vpermt2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	maskz_vpermt2b (predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > indices, simd< std::uint8_t, 32, Arch > b) noexcept
	Evaluate maskz_vpermt2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	vpermi2b (simd< std::uint8_t, 32, Arch > indices, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Evaluate vpermi2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	mask_vpermi2b (simd< std::uint8_t, 32, Arch > indices, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Evaluate mask_vpermi2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	maskz_vpermi2b (predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > indices, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Evaluate maskz_vpermi2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	vpmultishiftqb (simd< std::uint8_t, 32, Arch > control, simd< std::uint64_t, 4, Arch > value) noexcept
	Evaluate vpmultishiftqb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	mask_vpmultishiftqb (simd< std::uint8_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > control, simd< std::uint64_t, 4, Arch > value) noexcept
	Evaluate mask_vpmultishiftqb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	maskz_vpmultishiftqb (predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > control, simd< std::uint64_t, 4, Arch > value) noexcept
	Evaluate maskz_vpmultishiftqb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	vpermb (simd< std::uint8_t, 64, Arch > indices, simd< std::uint8_t, 64, Arch > value) noexcept
	Evaluate vpermb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	mask_vpermb (simd< std::uint8_t, 64, Arch > source, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > indices, simd< std::uint8_t, 64, Arch > value) noexcept
	Evaluate mask_vpermb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	maskz_vpermb (predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > indices, simd< std::uint8_t, 64, Arch > value) noexcept
	Evaluate maskz_vpermb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	vpermt2b (simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > indices, simd< std::uint8_t, 64, Arch > b) noexcept
	Evaluate vpermt2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	mask_vpermt2b (simd< std::uint8_t, 64, Arch > a, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > indices, simd< std::uint8_t, 64, Arch > b) noexcept
	Evaluate mask_vpermt2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	maskz_vpermt2b (predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > indices, simd< std::uint8_t, 64, Arch > b) noexcept
	Evaluate maskz_vpermt2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	vpermi2b (simd< std::uint8_t, 64, Arch > indices, simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept
	Evaluate vpermi2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	mask_vpermi2b (simd< std::uint8_t, 64, Arch > indices, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept
	Evaluate mask_vpermi2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	maskz_vpermi2b (predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > indices, simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept
	Evaluate maskz_vpermi2b at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	vpmultishiftqb (simd< std::uint8_t, 64, Arch > control, simd< std::uint64_t, 8, Arch > value) noexcept
	Evaluate vpmultishiftqb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	mask_vpmultishiftqb (simd< std::uint8_t, 64, Arch > source, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > control, simd< std::uint64_t, 8, Arch > value) noexcept
	Evaluate mask_vpmultishiftqb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	maskz_vpmultishiftqb (predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > control, simd< std::uint64_t, 8, Arch > value) noexcept
	Evaluate maskz_vpmultishiftqb at compile time when its register storage is available.
template<isa< x86 > Arch, class... Args>
void	vpermb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	mask_vpermb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	maskz_vpermb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	vpermt2b (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	mask_vpermt2b (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	maskz_vpermt2b (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	vpermi2b (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	mask_vpermi2b (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	maskz_vpermi2b (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	vpmultishiftqb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	mask_vpmultishiftqb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	maskz_vpmultishiftqb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	mask_vpcompressb (simd< std::uint8_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	maskz_vpcompressb (predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Remaining result lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr void	mask_vpcompressb (std::uint8_t *destination, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Store selected lanes in order; destination has popcount(mask) writable elements, or may be null if empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	mask_vpexpandb (simd< std::uint8_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	maskz_vpexpandb (predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Remaining result lanes become zero.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && (std::same_as<T, std::uint8_t> \|\| std::same_as<T, std::uint8_t const>))
constexpr simd< std::uint8_t, 16, Arch >	mask_vpexpandb (simd< std::uint8_t, 16, Arch > source, predicate< 16, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && (std::same_as<T, std::uint8_t> \|\| std::same_as<T, std::uint8_t const>))
constexpr simd< std::uint8_t, 16, Arch >	maskz_vpexpandb (predicate< 16, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	mask_vpcompressw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	maskz_vpcompressw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Remaining result lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr void	mask_vpcompressw (std::uint16_t *destination, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Store selected lanes in order; destination has popcount(mask) writable elements, or may be null if empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	mask_vpexpandw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	maskz_vpexpandw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Remaining result lanes become zero.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && (std::same_as<T, std::uint16_t> \|\| std::same_as<T, std::uint16_t const>))
constexpr simd< std::uint16_t, 8, Arch >	mask_vpexpandw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && (std::same_as<T, std::uint16_t> \|\| std::same_as<T, std::uint16_t const>))
constexpr simd< std::uint16_t, 8, Arch >	maskz_vpexpandw (predicate< 8, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 8, Arch >	vpshldw (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 8, Arch >	mask_vpshldw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 8, Arch >	maskz_vpshldw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	vpshldvw (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	mask_vpshldvw (simd< std::uint16_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	maskz_vpshldvw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 8, Arch >	vpshrdw (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 8, Arch >	mask_vpshrdw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 8, Arch >	maskz_vpshrdw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	vpshrdvw (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	mask_vpshrdvw (simd< std::uint16_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	maskz_vpshrdvw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 4, Arch >	vpshldd (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 4, Arch >	mask_vpshldd (simd< std::uint32_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 4, Arch >	maskz_vpshldd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	vpshldvd (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	mask_vpshldvd (simd< std::uint32_t, 4, Arch > a, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	maskz_vpshldvd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 4, Arch >	vpshrdd (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 4, Arch >	mask_vpshrdd (simd< std::uint32_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 4, Arch >	maskz_vpshrdd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	vpshrdvd (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	mask_vpshrdvd (simd< std::uint32_t, 4, Arch > a, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	maskz_vpshrdvd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 2, Arch >	vpshldq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 2, Arch >	mask_vpshldq (simd< std::uint64_t, 2, Arch > source, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 2, Arch >	maskz_vpshldq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	vpshldvq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	mask_vpshldvq (simd< std::uint64_t, 2, Arch > a, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	maskz_vpshldvq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 2, Arch >	vpshrdq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 2, Arch >	mask_vpshrdq (simd< std::uint64_t, 2, Arch > source, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 2, Arch >	maskz_vpshrdq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	vpshrdvq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	mask_vpshrdvq (simd< std::uint64_t, 2, Arch > a, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	maskz_vpshrdvq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	mask_vpcompressb (simd< std::uint8_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	maskz_vpcompressb (predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Remaining result lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr void	mask_vpcompressb (std::uint8_t *destination, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Store selected lanes in order; destination has popcount(mask) writable elements, or may be null if empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	mask_vpexpandb (simd< std::uint8_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	maskz_vpexpandb (predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Remaining result lanes become zero.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && (std::same_as<T, std::uint8_t> \|\| std::same_as<T, std::uint8_t const>))
constexpr simd< std::uint8_t, 32, Arch >	mask_vpexpandb (simd< std::uint8_t, 32, Arch > source, predicate< 32, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && (std::same_as<T, std::uint8_t> \|\| std::same_as<T, std::uint8_t const>))
constexpr simd< std::uint8_t, 32, Arch >	maskz_vpexpandb (predicate< 32, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	mask_vpcompressw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	maskz_vpcompressw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Remaining result lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr void	mask_vpcompressw (std::uint16_t *destination, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Store selected lanes in order; destination has popcount(mask) writable elements, or may be null if empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	mask_vpexpandw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	maskz_vpexpandw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Remaining result lanes become zero.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && (std::same_as<T, std::uint16_t> \|\| std::same_as<T, std::uint16_t const>))
constexpr simd< std::uint16_t, 16, Arch >	mask_vpexpandw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && (std::same_as<T, std::uint16_t> \|\| std::same_as<T, std::uint16_t const>))
constexpr simd< std::uint16_t, 16, Arch >	maskz_vpexpandw (predicate< 16, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 16, Arch >	vpshldw (simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 16, Arch >	mask_vpshldw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 16, Arch >	maskz_vpshldw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	vpshldvw (simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	mask_vpshldvw (simd< std::uint16_t, 16, Arch > a, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	maskz_vpshldvw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 16, Arch >	vpshrdw (simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 16, Arch >	mask_vpshrdw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 16, Arch >	maskz_vpshrdw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	vpshrdvw (simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	mask_vpshrdvw (simd< std::uint16_t, 16, Arch > a, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	maskz_vpshrdvw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 8, Arch >	vpshldd (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 8, Arch >	mask_vpshldd (simd< std::uint32_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 8, Arch >	maskz_vpshldd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	vpshldvd (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	mask_vpshldvd (simd< std::uint32_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	maskz_vpshldvd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 8, Arch >	vpshrdd (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 8, Arch >	mask_vpshrdd (simd< std::uint32_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 8, Arch >	maskz_vpshrdd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	vpshrdvd (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	mask_vpshrdvd (simd< std::uint32_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	maskz_vpshrdvd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 4, Arch >	vpshldq (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 4, Arch >	mask_vpshldq (simd< std::uint64_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 4, Arch >	maskz_vpshldq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	vpshldvq (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	mask_vpshldvq (simd< std::uint64_t, 4, Arch > a, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	maskz_vpshldvq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 4, Arch >	vpshrdq (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 4, Arch >	mask_vpshrdq (simd< std::uint64_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 4, Arch >	maskz_vpshrdq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	vpshrdvq (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	mask_vpshrdvq (simd< std::uint64_t, 4, Arch > a, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	maskz_vpshrdvq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint8_t, 64, Arch >	mask_vpcompressb (simd< std::uint8_t, 64, Arch > source, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint8_t, 64, Arch >	maskz_vpcompressb (predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Remaining result lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr void	mask_vpcompressb (std::uint8_t *destination, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Store selected lanes in order; destination has popcount(mask) writable elements, or may be null if empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint8_t, 64, Arch >	mask_vpexpandb (simd< std::uint8_t, 64, Arch > source, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint8_t, 64, Arch >	maskz_vpexpandb (predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Remaining result lanes become zero.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && (std::same_as<T, std::uint8_t> \|\| std::same_as<T, std::uint8_t const>))
constexpr simd< std::uint8_t, 64, Arch >	mask_vpexpandb (simd< std::uint8_t, 64, Arch > source, predicate< 64, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && (std::same_as<T, std::uint8_t> \|\| std::same_as<T, std::uint8_t const>))
constexpr simd< std::uint8_t, 64, Arch >	maskz_vpexpandb (predicate< 64, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	mask_vpcompressw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	maskz_vpcompressw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Remaining result lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr void	mask_vpcompressw (std::uint16_t *destination, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Store selected lanes in order; destination has popcount(mask) writable elements, or may be null if empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	mask_vpexpandw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	maskz_vpexpandw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Remaining result lanes become zero.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && (std::same_as<T, std::uint16_t> \|\| std::same_as<T, std::uint16_t const>))
constexpr simd< std::uint16_t, 32, Arch >	mask_vpexpandw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && (std::same_as<T, std::uint16_t> \|\| std::same_as<T, std::uint16_t const>))
constexpr simd< std::uint16_t, 32, Arch >	maskz_vpexpandw (predicate< 32, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint16_t, 32, Arch >	vpshldw (simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint16_t, 32, Arch >	mask_vpshldw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint16_t, 32, Arch >	maskz_vpshldw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	vpshldvw (simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	mask_vpshldvw (simd< std::uint16_t, 32, Arch > a, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	maskz_vpshldvw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint16_t, 32, Arch >	vpshrdw (simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint16_t, 32, Arch >	mask_vpshrdw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint16_t, 32, Arch >	maskz_vpshrdw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	vpshrdvw (simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	mask_vpshrdvw (simd< std::uint16_t, 32, Arch > a, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	maskz_vpshrdvw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint32_t, 16, Arch >	vpshldd (simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint32_t, 16, Arch >	mask_vpshldd (simd< std::uint32_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint32_t, 16, Arch >	maskz_vpshldd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint32_t, 16, Arch >	vpshldvd (simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint32_t, 16, Arch >	mask_vpshldvd (simd< std::uint32_t, 16, Arch > a, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint32_t, 16, Arch >	maskz_vpshldvd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint32_t, 16, Arch >	vpshrdd (simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint32_t, 16, Arch >	mask_vpshrdd (simd< std::uint32_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint32_t, 16, Arch >	maskz_vpshrdd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint32_t, 16, Arch >	vpshrdvd (simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint32_t, 16, Arch >	mask_vpshrdvd (simd< std::uint32_t, 16, Arch > a, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint32_t, 16, Arch >	maskz_vpshrdvd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint64_t, 8, Arch >	vpshldq (simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint64_t, 8, Arch >	mask_vpshldq (simd< std::uint64_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint64_t, 8, Arch >	maskz_vpshldq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint64_t, 8, Arch >	vpshldvq (simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint64_t, 8, Arch >	mask_vpshldvq (simd< std::uint64_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint64_t, 8, Arch >	maskz_vpshldvq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint64_t, 8, Arch >	vpshrdq (simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint64_t, 8, Arch >	mask_vpshrdq (simd< std::uint64_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint64_t, 8, Arch >	maskz_vpshrdq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint64_t, 8, Arch >	vpshrdvq (simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint64_t, 8, Arch >	mask_vpshrdvq (simd< std::uint64_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint64_t, 8, Arch >	maskz_vpshrdvq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	mask_vpcompressb (simd< std::uint8_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Evaluate mask_vpcompressb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	maskz_vpcompressb (predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Evaluate maskz_vpcompressb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval void	mask_vpcompressb (std::uint8_t *destination, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Evaluate mask_vpcompressb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	mask_vpexpandb (simd< std::uint8_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Evaluate mask_vpexpandb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	maskz_vpexpandb (predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Evaluate maskz_vpexpandb at compile time when its register storage is available.
template<isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && (std::same_as<T, std::uint8_t> \|\| std::same_as<T, std::uint8_t const>) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	mask_vpexpandb (simd< std::uint8_t, 16, Arch > source, predicate< 16, Arch > maskmask, T *memory) noexcept
	Evaluate mask_vpexpandb at compile time when its register storage is available.
template<isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && (std::same_as<T, std::uint8_t> \|\| std::same_as<T, std::uint8_t const>) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint8_t, 16, Arch >	maskz_vpexpandb (predicate< 16, Arch > maskmask, T *memory) noexcept
	Evaluate maskz_vpexpandb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	mask_vpcompressw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Evaluate mask_vpcompressw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	maskz_vpcompressw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Evaluate maskz_vpcompressw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval void	mask_vpcompressw (std::uint16_t *destination, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Evaluate mask_vpcompressw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	mask_vpexpandw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Evaluate mask_vpexpandw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	maskz_vpexpandw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Evaluate maskz_vpexpandw at compile time when its register storage is available.
template<isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && (std::same_as<T, std::uint16_t> \|\| std::same_as<T, std::uint16_t const>) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	mask_vpexpandw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, T *memory) noexcept
	Evaluate mask_vpexpandw at compile time when its register storage is available.
template<isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && (std::same_as<T, std::uint16_t> \|\| std::same_as<T, std::uint16_t const>) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	maskz_vpexpandw (predicate< 8, Arch > maskmask, T *memory) noexcept
	Evaluate maskz_vpexpandw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	vpshldw (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Evaluate vpshldw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	mask_vpshldw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Evaluate mask_vpshldw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	maskz_vpshldw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Evaluate maskz_vpshldw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	vpshldvw (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Evaluate vpshldvw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	mask_vpshldvw (simd< std::uint16_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Evaluate mask_vpshldvw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	maskz_vpshldvw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Evaluate maskz_vpshldvw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	vpshrdw (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Evaluate vpshrdw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	mask_vpshrdw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Evaluate mask_vpshrdw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	maskz_vpshrdw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Evaluate maskz_vpshrdw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	vpshrdvw (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Evaluate vpshrdvw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	mask_vpshrdvw (simd< std::uint16_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Evaluate mask_vpshrdvw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint16_t, 8, Arch >	maskz_vpshrdvw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Evaluate maskz_vpshrdvw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	vpshldd (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Evaluate vpshldd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	mask_vpshldd (simd< std::uint32_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Evaluate mask_vpshldd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	maskz_vpshldd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Evaluate maskz_vpshldd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	vpshldvd (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Evaluate vpshldvd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	mask_vpshldvd (simd< std::uint32_t, 4, Arch > a, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Evaluate mask_vpshldvd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	maskz_vpshldvd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Evaluate maskz_vpshldvd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	vpshrdd (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Evaluate vpshrdd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	mask_vpshrdd (simd< std::uint32_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Evaluate mask_vpshrdd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	maskz_vpshrdd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Evaluate maskz_vpshrdd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	vpshrdvd (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Evaluate vpshrdvd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	mask_vpshrdvd (simd< std::uint32_t, 4, Arch > a, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Evaluate mask_vpshrdvd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	maskz_vpshrdvd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Evaluate maskz_vpshrdvd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	vpshldq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Evaluate vpshldq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	mask_vpshldq (simd< std::uint64_t, 2, Arch > source, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Evaluate mask_vpshldq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	maskz_vpshldq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Evaluate maskz_vpshldq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	vpshldvq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Evaluate vpshldvq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	mask_vpshldvq (simd< std::uint64_t, 2, Arch > a, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Evaluate mask_vpshldvq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	maskz_vpshldvq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Evaluate maskz_vpshldvq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	vpshrdq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Evaluate vpshrdq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	mask_vpshrdq (simd< std::uint64_t, 2, Arch > source, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Evaluate mask_vpshrdq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	maskz_vpshrdq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Evaluate maskz_vpshrdq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	vpshrdvq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Evaluate vpshrdvq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	mask_vpshrdvq (simd< std::uint64_t, 2, Arch > a, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Evaluate mask_vpshrdvq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	maskz_vpshrdvq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Evaluate maskz_vpshrdvq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	mask_vpcompressb (simd< std::uint8_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Evaluate mask_vpcompressb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	maskz_vpcompressb (predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Evaluate maskz_vpcompressb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval void	mask_vpcompressb (std::uint8_t *destination, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Evaluate mask_vpcompressb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	mask_vpexpandb (simd< std::uint8_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Evaluate mask_vpexpandb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	maskz_vpexpandb (predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Evaluate maskz_vpexpandb at compile time when its register storage is available.
template<isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && (std::same_as<T, std::uint8_t> \|\| std::same_as<T, std::uint8_t const>) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	mask_vpexpandb (simd< std::uint8_t, 32, Arch > source, predicate< 32, Arch > maskmask, T *memory) noexcept
	Evaluate mask_vpexpandb at compile time when its register storage is available.
template<isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && (std::same_as<T, std::uint8_t> \|\| std::same_as<T, std::uint8_t const>) && requires { sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint8_t, 32, Arch >	maskz_vpexpandb (predicate< 32, Arch > maskmask, T *memory) noexcept
	Evaluate maskz_vpexpandb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	mask_vpcompressw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Evaluate mask_vpcompressw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	maskz_vpcompressw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Evaluate maskz_vpcompressw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval void	mask_vpcompressw (std::uint16_t *destination, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Evaluate mask_vpcompressw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	mask_vpexpandw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Evaluate mask_vpexpandw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	maskz_vpexpandw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Evaluate maskz_vpexpandw at compile time when its register storage is available.
template<isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && (std::same_as<T, std::uint16_t> \|\| std::same_as<T, std::uint16_t const>) && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	mask_vpexpandw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, T *memory) noexcept
	Evaluate mask_vpexpandw at compile time when its register storage is available.
template<isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && (std::same_as<T, std::uint16_t> \|\| std::same_as<T, std::uint16_t const>) && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	maskz_vpexpandw (predicate< 16, Arch > maskmask, T *memory) noexcept
	Evaluate maskz_vpexpandw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	vpshldw (simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Evaluate vpshldw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	mask_vpshldw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Evaluate mask_vpshldw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	maskz_vpshldw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Evaluate maskz_vpshldw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	vpshldvw (simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Evaluate vpshldvw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	mask_vpshldvw (simd< std::uint16_t, 16, Arch > a, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Evaluate mask_vpshldvw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	maskz_vpshldvw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Evaluate maskz_vpshldvw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	vpshrdw (simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Evaluate vpshrdw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	mask_vpshrdw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Evaluate mask_vpshrdw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	maskz_vpshrdw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Evaluate maskz_vpshrdw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	vpshrdvw (simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Evaluate vpshrdvw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	mask_vpshrdvw (simd< std::uint16_t, 16, Arch > a, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Evaluate mask_vpshrdvw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint16_t, 16, Arch >	maskz_vpshrdvw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Evaluate maskz_vpshrdvw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	vpshldd (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Evaluate vpshldd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	mask_vpshldd (simd< std::uint32_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Evaluate mask_vpshldd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	maskz_vpshldd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Evaluate maskz_vpshldd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	vpshldvd (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Evaluate vpshldvd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	mask_vpshldvd (simd< std::uint32_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Evaluate mask_vpshldvd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	maskz_vpshldvd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Evaluate maskz_vpshldvd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	vpshrdd (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Evaluate vpshrdd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	mask_vpshrdd (simd< std::uint32_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Evaluate mask_vpshrdd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	maskz_vpshrdd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Evaluate maskz_vpshrdd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	vpshrdvd (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Evaluate vpshrdvd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	mask_vpshrdvd (simd< std::uint32_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Evaluate mask_vpshrdvd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	maskz_vpshrdvd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Evaluate maskz_vpshrdvd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	vpshldq (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Evaluate vpshldq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	mask_vpshldq (simd< std::uint64_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Evaluate mask_vpshldq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	maskz_vpshldq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Evaluate maskz_vpshldq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	vpshldvq (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Evaluate vpshldvq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	mask_vpshldvq (simd< std::uint64_t, 4, Arch > a, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Evaluate mask_vpshldvq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	maskz_vpshldvq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Evaluate maskz_vpshldvq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	vpshrdq (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Evaluate vpshrdq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	mask_vpshrdq (simd< std::uint64_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Evaluate mask_vpshrdq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	maskz_vpshrdq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Evaluate maskz_vpshrdq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	vpshrdvq (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Evaluate vpshrdvq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	mask_vpshrdvq (simd< std::uint64_t, 4, Arch > a, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Evaluate mask_vpshrdvq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl)) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	maskz_vpshrdvq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Evaluate maskz_vpshrdvq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	mask_vpcompressb (simd< std::uint8_t, 64, Arch > source, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Evaluate mask_vpcompressb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	maskz_vpcompressb (predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Evaluate maskz_vpcompressb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval void	mask_vpcompressb (std::uint8_t *destination, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Evaluate mask_vpcompressb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	mask_vpexpandb (simd< std::uint8_t, 64, Arch > source, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Evaluate mask_vpexpandb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	maskz_vpexpandb (predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Evaluate maskz_vpexpandb at compile time when its register storage is available.
template<isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && (std::same_as<T, std::uint8_t> \|\| std::same_as<T, std::uint8_t const>) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	mask_vpexpandb (simd< std::uint8_t, 64, Arch > source, predicate< 64, Arch > maskmask, T *memory) noexcept
	Evaluate mask_vpexpandb at compile time when its register storage is available.
template<isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && (std::same_as<T, std::uint8_t> \|\| std::same_as<T, std::uint8_t const>) && requires { sizeof(simd<std::uint8_t, 64, Arch>); })
consteval simd< std::uint8_t, 64, Arch >	maskz_vpexpandb (predicate< 64, Arch > maskmask, T *memory) noexcept
	Evaluate maskz_vpexpandb at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	mask_vpcompressw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Evaluate mask_vpcompressw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	maskz_vpcompressw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Evaluate maskz_vpcompressw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval void	mask_vpcompressw (std::uint16_t *destination, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Evaluate mask_vpcompressw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	mask_vpexpandw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Evaluate mask_vpexpandw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	maskz_vpexpandw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Evaluate maskz_vpexpandw at compile time when its register storage is available.
template<isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && (std::same_as<T, std::uint16_t> \|\| std::same_as<T, std::uint16_t const>) && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	mask_vpexpandw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, T *memory) noexcept
	Evaluate mask_vpexpandw at compile time when its register storage is available.
template<isa< x86 > Arch, class T> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && (std::same_as<T, std::uint16_t> \|\| std::same_as<T, std::uint16_t const>) && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	maskz_vpexpandw (predicate< 32, Arch > maskmask, T *memory) noexcept
	Evaluate maskz_vpexpandw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	vpshldw (simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Evaluate vpshldw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	mask_vpshldw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Evaluate mask_vpshldw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	maskz_vpshldw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Evaluate maskz_vpshldw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	vpshldvw (simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Evaluate vpshldvw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	mask_vpshldvw (simd< std::uint16_t, 32, Arch > a, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Evaluate mask_vpshldvw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	maskz_vpshldvw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Evaluate maskz_vpshldvw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	vpshrdw (simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Evaluate vpshrdw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	mask_vpshrdw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Evaluate mask_vpshrdw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	maskz_vpshrdw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Evaluate maskz_vpshrdw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	vpshrdvw (simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Evaluate vpshrdvw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	mask_vpshrdvw (simd< std::uint16_t, 32, Arch > a, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Evaluate mask_vpshrdvw at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint16_t, 32, Arch>); })
consteval simd< std::uint16_t, 32, Arch >	maskz_vpshrdvw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Evaluate maskz_vpshrdvw at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	vpshldd (simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Evaluate vpshldd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	mask_vpshldd (simd< std::uint32_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Evaluate mask_vpshldd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	maskz_vpshldd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Evaluate maskz_vpshldd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	vpshldvd (simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Evaluate vpshldvd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	mask_vpshldvd (simd< std::uint32_t, 16, Arch > a, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Evaluate mask_vpshldvd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	maskz_vpshldvd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Evaluate maskz_vpshldvd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	vpshrdd (simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Evaluate vpshrdd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	mask_vpshrdd (simd< std::uint32_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Evaluate mask_vpshrdd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	maskz_vpshrdd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Evaluate maskz_vpshrdd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	vpshrdvd (simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Evaluate vpshrdvd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	mask_vpshrdvd (simd< std::uint32_t, 16, Arch > a, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Evaluate mask_vpshrdvd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	maskz_vpshrdvd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Evaluate maskz_vpshrdvd at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	vpshldq (simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Evaluate vpshldq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	mask_vpshldq (simd< std::uint64_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Evaluate mask_vpshldq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	maskz_vpshldq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Evaluate maskz_vpshldq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	vpshldvq (simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Evaluate vpshldvq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	mask_vpshldvq (simd< std::uint64_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Evaluate mask_vpshldvq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	maskz_vpshldvq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Evaluate maskz_vpshldvq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	vpshrdq (simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Evaluate vpshrdq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	mask_vpshrdq (simd< std::uint64_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Evaluate mask_vpshrdq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	maskz_vpshrdq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Evaluate maskz_vpshrdq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	vpshrdvq (simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Evaluate vpshrdvq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	mask_vpshrdvq (simd< std::uint64_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Evaluate mask_vpshrdvq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!(Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2)) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	maskz_vpshrdvq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Evaluate maskz_vpshrdvq at compile time when its register storage is available.
template<isa< x86 > Arch, class... Args>
void	mask_vpcompressb (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	maskz_vpcompressb (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	mask_vpexpandb (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	maskz_vpexpandb (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	mask_vpcompressw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	maskz_vpcompressw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	mask_vpexpandw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	maskz_vpexpandw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	vpshldw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	mask_vpshldw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	maskz_vpshldw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	vpshldvw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	mask_vpshldvw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	maskz_vpshldvw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	vpshrdw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	mask_vpshrdw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	maskz_vpshrdw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	vpshrdvw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	mask_vpshrdvw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	maskz_vpshrdvw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	vpshldd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	mask_vpshldd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	maskz_vpshldd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	vpshldvd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	mask_vpshldvd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	maskz_vpshldvd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	vpshrdd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	mask_vpshrdd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	maskz_vpshrdd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	vpshrdvd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	mask_vpshrdvd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	maskz_vpshrdvd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	vpshldq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	mask_vpshldq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	maskz_vpshldq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	vpshldvq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	mask_vpshldvq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	maskz_vpshldvq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	vpshrdq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	mask_vpshrdq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	maskz_vpshrdq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	vpshrdvq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	mask_vpshrdvq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	maskz_vpshrdvq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnni))
constexpr simd< std::int32_t, 4, Arch >	dpbusd (simd< std::int32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Accumulate products of four unsigned bytes from a and signed bytes from b, modulo 2^32. Uses AVX-VNNI.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::avxvnni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 4, Arch >	dpbusd (simd< std::int32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Accumulate products of four unsigned bytes from a and signed bytes from b, modulo 2^32. Uses AVX512VNNI.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 4, Arch >	mask_dpbusd (simd< std::int32_t, 4, Arch > accumulator, predicate< 4, Arch > maskmask, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	dpbusd in active lanes; inactive lanes retain accumulator.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 4, Arch >	maskz_dpbusd (predicate< 4, Arch > maskmask, simd< std::int32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	dpbusd in active lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnni))
constexpr simd< std::int32_t, 4, Arch >	dpbusds (simd< std::int32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Accumulate products of four unsigned bytes from a and signed bytes from b, with signed 32-bit saturation. Uses AVX-VNNI.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::avxvnni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 4, Arch >	dpbusds (simd< std::int32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Accumulate products of four unsigned bytes from a and signed bytes from b, with signed 32-bit saturation. Uses AVX512VNNI.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 4, Arch >	mask_dpbusds (simd< std::int32_t, 4, Arch > accumulator, predicate< 4, Arch > maskmask, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	dpbusds in active lanes; inactive lanes retain accumulator.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 4, Arch >	maskz_dpbusds (predicate< 4, Arch > maskmask, simd< std::int32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	dpbusds in active lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnni))
constexpr simd< std::int32_t, 4, Arch >	dpwssd (simd< std::int32_t, 4, Arch > accumulator, simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	Accumulate products of two signed words from a and b, modulo 2^32. Uses AVX-VNNI.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::avxvnni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 4, Arch >	dpwssd (simd< std::int32_t, 4, Arch > accumulator, simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	Accumulate products of two signed words from a and b, modulo 2^32. Uses AVX512VNNI.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 4, Arch >	mask_dpwssd (simd< std::int32_t, 4, Arch > accumulator, predicate< 4, Arch > maskmask, simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	dpwssd in active lanes; inactive lanes retain accumulator.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 4, Arch >	maskz_dpwssd (predicate< 4, Arch > maskmask, simd< std::int32_t, 4, Arch > accumulator, simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	dpwssd in active lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnni))
constexpr simd< std::int32_t, 4, Arch >	dpwssds (simd< std::int32_t, 4, Arch > accumulator, simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	Accumulate products of two signed words from a and b, with signed 32-bit saturation. Uses AVX-VNNI.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::avxvnni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 4, Arch >	dpwssds (simd< std::int32_t, 4, Arch > accumulator, simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	Accumulate products of two signed words from a and b, with signed 32-bit saturation. Uses AVX512VNNI.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 4, Arch >	mask_dpwssds (simd< std::int32_t, 4, Arch > accumulator, predicate< 4, Arch > maskmask, simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	dpwssds in active lanes; inactive lanes retain accumulator.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 4, Arch >	maskz_dpwssds (predicate< 4, Arch > maskmask, simd< std::int32_t, 4, Arch > accumulator, simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	dpwssds in active lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnni))
constexpr simd< std::int32_t, 8, Arch >	dpbusd (simd< std::int32_t, 8, Arch > accumulator, simd< std::uint8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	Accumulate products of four unsigned bytes from a and signed bytes from b, modulo 2^32. Uses AVX-VNNI.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::avxvnni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 8, Arch >	dpbusd (simd< std::int32_t, 8, Arch > accumulator, simd< std::uint8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	Accumulate products of four unsigned bytes from a and signed bytes from b, modulo 2^32. Uses AVX512VNNI.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 8, Arch >	mask_dpbusd (simd< std::int32_t, 8, Arch > accumulator, predicate< 8, Arch > maskmask, simd< std::uint8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	dpbusd in active lanes; inactive lanes retain accumulator.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 8, Arch >	maskz_dpbusd (predicate< 8, Arch > maskmask, simd< std::int32_t, 8, Arch > accumulator, simd< std::uint8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	dpbusd in active lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnni))
constexpr simd< std::int32_t, 8, Arch >	dpbusds (simd< std::int32_t, 8, Arch > accumulator, simd< std::uint8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	Accumulate products of four unsigned bytes from a and signed bytes from b, with signed 32-bit saturation. Uses AVX-VNNI.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::avxvnni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 8, Arch >	dpbusds (simd< std::int32_t, 8, Arch > accumulator, simd< std::uint8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	Accumulate products of four unsigned bytes from a and signed bytes from b, with signed 32-bit saturation. Uses AVX512VNNI.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 8, Arch >	mask_dpbusds (simd< std::int32_t, 8, Arch > accumulator, predicate< 8, Arch > maskmask, simd< std::uint8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	dpbusds in active lanes; inactive lanes retain accumulator.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 8, Arch >	maskz_dpbusds (predicate< 8, Arch > maskmask, simd< std::int32_t, 8, Arch > accumulator, simd< std::uint8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	dpbusds in active lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnni))
constexpr simd< std::int32_t, 8, Arch >	dpwssd (simd< std::int32_t, 8, Arch > accumulator, simd< std::int16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	Accumulate products of two signed words from a and b, modulo 2^32. Uses AVX-VNNI.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::avxvnni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 8, Arch >	dpwssd (simd< std::int32_t, 8, Arch > accumulator, simd< std::int16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	Accumulate products of two signed words from a and b, modulo 2^32. Uses AVX512VNNI.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 8, Arch >	mask_dpwssd (simd< std::int32_t, 8, Arch > accumulator, predicate< 8, Arch > maskmask, simd< std::int16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	dpwssd in active lanes; inactive lanes retain accumulator.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 8, Arch >	maskz_dpwssd (predicate< 8, Arch > maskmask, simd< std::int32_t, 8, Arch > accumulator, simd< std::int16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	dpwssd in active lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnni))
constexpr simd< std::int32_t, 8, Arch >	dpwssds (simd< std::int32_t, 8, Arch > accumulator, simd< std::int16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	Accumulate products of two signed words from a and b, with signed 32-bit saturation. Uses AVX-VNNI.
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::avxvnni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 8, Arch >	dpwssds (simd< std::int32_t, 8, Arch > accumulator, simd< std::int16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	Accumulate products of two signed words from a and b, with signed 32-bit saturation. Uses AVX512VNNI.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 8, Arch >	mask_dpwssds (simd< std::int32_t, 8, Arch > accumulator, predicate< 8, Arch > maskmask, simd< std::int16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	dpwssds in active lanes; inactive lanes retain accumulator.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::int32_t, 8, Arch >	maskz_dpwssds (predicate< 8, Arch > maskmask, simd< std::int32_t, 8, Arch > accumulator, simd< std::int16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	dpwssds in active lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))
constexpr simd< std::int32_t, 16, Arch >	dpbusd (simd< std::int32_t, 16, Arch > accumulator, simd< std::uint8_t, 64, Arch > a, simd< std::int8_t, 64, Arch > b) noexcept
	Accumulate products of four unsigned bytes from a and signed bytes from b, modulo 2^32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))
constexpr simd< std::int32_t, 16, Arch >	mask_dpbusd (simd< std::int32_t, 16, Arch > accumulator, predicate< 16, Arch > maskmask, simd< std::uint8_t, 64, Arch > a, simd< std::int8_t, 64, Arch > b) noexcept
	dpbusd in active lanes; inactive lanes retain accumulator.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))
constexpr simd< std::int32_t, 16, Arch >	maskz_dpbusd (predicate< 16, Arch > maskmask, simd< std::int32_t, 16, Arch > accumulator, simd< std::uint8_t, 64, Arch > a, simd< std::int8_t, 64, Arch > b) noexcept
	dpbusd in active lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))
constexpr simd< std::int32_t, 16, Arch >	dpbusds (simd< std::int32_t, 16, Arch > accumulator, simd< std::uint8_t, 64, Arch > a, simd< std::int8_t, 64, Arch > b) noexcept
	Accumulate products of four unsigned bytes from a and signed bytes from b, with signed 32-bit saturation.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))
constexpr simd< std::int32_t, 16, Arch >	mask_dpbusds (simd< std::int32_t, 16, Arch > accumulator, predicate< 16, Arch > maskmask, simd< std::uint8_t, 64, Arch > a, simd< std::int8_t, 64, Arch > b) noexcept
	dpbusds in active lanes; inactive lanes retain accumulator.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))
constexpr simd< std::int32_t, 16, Arch >	maskz_dpbusds (predicate< 16, Arch > maskmask, simd< std::int32_t, 16, Arch > accumulator, simd< std::uint8_t, 64, Arch > a, simd< std::int8_t, 64, Arch > b) noexcept
	dpbusds in active lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))
constexpr simd< std::int32_t, 16, Arch >	dpwssd (simd< std::int32_t, 16, Arch > accumulator, simd< std::int16_t, 32, Arch > a, simd< std::int16_t, 32, Arch > b) noexcept
	Accumulate products of two signed words from a and b, modulo 2^32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))
constexpr simd< std::int32_t, 16, Arch >	mask_dpwssd (simd< std::int32_t, 16, Arch > accumulator, predicate< 16, Arch > maskmask, simd< std::int16_t, 32, Arch > a, simd< std::int16_t, 32, Arch > b) noexcept
	dpwssd in active lanes; inactive lanes retain accumulator.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))
constexpr simd< std::int32_t, 16, Arch >	maskz_dpwssd (predicate< 16, Arch > maskmask, simd< std::int32_t, 16, Arch > accumulator, simd< std::int16_t, 32, Arch > a, simd< std::int16_t, 32, Arch > b) noexcept
	dpwssd in active lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))
constexpr simd< std::int32_t, 16, Arch >	dpwssds (simd< std::int32_t, 16, Arch > accumulator, simd< std::int16_t, 32, Arch > a, simd< std::int16_t, 32, Arch > b) noexcept
	Accumulate products of two signed words from a and b, with signed 32-bit saturation.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))
constexpr simd< std::int32_t, 16, Arch >	mask_dpwssds (simd< std::int32_t, 16, Arch > accumulator, predicate< 16, Arch > maskmask, simd< std::int16_t, 32, Arch > a, simd< std::int16_t, 32, Arch > b) noexcept
	dpwssds in active lanes; inactive lanes retain accumulator.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))
constexpr simd< std::int32_t, 16, Arch >	maskz_dpwssds (predicate< 16, Arch > maskmask, simd< std::int32_t, 16, Arch > accumulator, simd< std::int16_t, 32, Arch > a, simd< std::int16_t, 32, Arch > b) noexcept
	dpwssds in active lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint8))
constexpr simd< std::int32_t, 4, Arch >	dpbssd (simd< std::int32_t, 4, Arch > accumulator, simd< std::int8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Accumulate products of four signed bytes from a and b, modulo 2^32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint8))
constexpr simd< std::int32_t, 8, Arch >	dpbssd (simd< std::int32_t, 8, Arch > accumulator, simd< std::int8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	Accumulate products of four signed bytes from a and b, modulo 2^32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint8))
constexpr simd< std::int32_t, 4, Arch >	dpbssds (simd< std::int32_t, 4, Arch > accumulator, simd< std::int8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Accumulate products of four signed bytes from a and b, with signed 32-bit saturation.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint8))
constexpr simd< std::int32_t, 8, Arch >	dpbssds (simd< std::int32_t, 8, Arch > accumulator, simd< std::int8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	Accumulate products of four signed bytes from a and b, with signed 32-bit saturation.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint8))
constexpr simd< std::int32_t, 4, Arch >	dpbsud (simd< std::int32_t, 4, Arch > accumulator, simd< std::int8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Accumulate products of four signed bytes from a and unsigned bytes from b, modulo 2^32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint8))
constexpr simd< std::int32_t, 8, Arch >	dpbsud (simd< std::int32_t, 8, Arch > accumulator, simd< std::int8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Accumulate products of four signed bytes from a and unsigned bytes from b, modulo 2^32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint8))
constexpr simd< std::int32_t, 4, Arch >	dpbsuds (simd< std::int32_t, 4, Arch > accumulator, simd< std::int8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Accumulate products of four signed bytes from a and unsigned bytes from b, with signed 32-bit saturation.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint8))
constexpr simd< std::int32_t, 8, Arch >	dpbsuds (simd< std::int32_t, 8, Arch > accumulator, simd< std::int8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Accumulate products of four signed bytes from a and unsigned bytes from b, with signed 32-bit saturation.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint8))
constexpr simd< std::uint32_t, 4, Arch >	dpbuud (simd< std::uint32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Accumulate products of four unsigned bytes from a and b, modulo 2^32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint8))
constexpr simd< std::uint32_t, 8, Arch >	dpbuud (simd< std::uint32_t, 8, Arch > accumulator, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Accumulate products of four unsigned bytes from a and b, modulo 2^32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint8))
constexpr simd< std::uint32_t, 4, Arch >	dpbuuds (simd< std::uint32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Accumulate products of four unsigned bytes from a and b, with unsigned 32-bit saturation.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint8))
constexpr simd< std::uint32_t, 8, Arch >	dpbuuds (simd< std::uint32_t, 8, Arch > accumulator, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Accumulate products of four unsigned bytes from a and b, with unsigned 32-bit saturation.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint16))
constexpr simd< std::int32_t, 4, Arch >	dpwsud (simd< std::int32_t, 4, Arch > accumulator, simd< std::int16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Accumulate products of two signed words from a and unsigned words from b, modulo 2^32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint16))
constexpr simd< std::int32_t, 8, Arch >	dpwsud (simd< std::int32_t, 8, Arch > accumulator, simd< std::int16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Accumulate products of two signed words from a and unsigned words from b, modulo 2^32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint16))
constexpr simd< std::int32_t, 4, Arch >	dpwsuds (simd< std::int32_t, 4, Arch > accumulator, simd< std::int16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Accumulate products of two signed words from a and unsigned words from b, with signed 32-bit saturation.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint16))
constexpr simd< std::int32_t, 8, Arch >	dpwsuds (simd< std::int32_t, 8, Arch > accumulator, simd< std::int16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Accumulate products of two signed words from a and unsigned words from b, with signed 32-bit saturation.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint16))
constexpr simd< std::int32_t, 4, Arch >	dpwusd (simd< std::int32_t, 4, Arch > accumulator, simd< std::uint16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	Accumulate products of two unsigned words from a and signed words from b, modulo 2^32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint16))
constexpr simd< std::int32_t, 8, Arch >	dpwusd (simd< std::int32_t, 8, Arch > accumulator, simd< std::uint16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	Accumulate products of two unsigned words from a and signed words from b, modulo 2^32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint16))
constexpr simd< std::int32_t, 4, Arch >	dpwusds (simd< std::int32_t, 4, Arch > accumulator, simd< std::uint16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	Accumulate products of two unsigned words from a and signed words from b, with signed 32-bit saturation.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint16))
constexpr simd< std::int32_t, 8, Arch >	dpwusds (simd< std::int32_t, 8, Arch > accumulator, simd< std::uint16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	Accumulate products of two unsigned words from a and signed words from b, with signed 32-bit saturation.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint16))
constexpr simd< std::uint32_t, 4, Arch >	dpwuud (simd< std::uint32_t, 4, Arch > accumulator, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Accumulate products of two unsigned words from a and b, modulo 2^32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint16))
constexpr simd< std::uint32_t, 8, Arch >	dpwuud (simd< std::uint32_t, 8, Arch > accumulator, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Accumulate products of two unsigned words from a and b, modulo 2^32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint16))
constexpr simd< std::uint32_t, 4, Arch >	dpwuuds (simd< std::uint32_t, 4, Arch > accumulator, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Accumulate products of two unsigned words from a and b, with unsigned 32-bit saturation.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxvnniint16))
constexpr simd< std::uint32_t, 8, Arch >	dpwuuds (simd< std::uint32_t, 8, Arch > accumulator, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Accumulate products of two unsigned words from a and b, with unsigned 32-bit saturation.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnni)) \|\| (!Arch.has(x86_feature::avxvnni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::uint8_t, 16, Arch> ); sizeof(simd<std::int8_t, 16, Arch>); })
consteval simd< std::int32_t, 4, Arch >	dpbusd (simd< std::int32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Evaluate dpbusd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd<std::int8_t, 16, Arch>); })
consteval simd< std::int32_t, 4, Arch >	mask_dpbusd (simd< std::int32_t, 4, Arch > accumulator, predicate< 4, Arch > maskmask, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Evaluate mask_dpbusd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd<std::int8_t, 16, Arch>); })
consteval simd< std::int32_t, 4, Arch >	maskz_dpbusd (predicate< 4, Arch > maskmask, simd< std::int32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Evaluate maskz_dpbusd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnni)) \|\| (!Arch.has(x86_feature::avxvnni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::uint8_t, 16, Arch> ); sizeof(simd<std::int8_t, 16, Arch>); })
consteval simd< std::int32_t, 4, Arch >	dpbusds (simd< std::int32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Evaluate dpbusds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd<std::int8_t, 16, Arch>); })
consteval simd< std::int32_t, 4, Arch >	mask_dpbusds (simd< std::int32_t, 4, Arch > accumulator, predicate< 4, Arch > maskmask, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Evaluate mask_dpbusds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd<std::int8_t, 16, Arch>); })
consteval simd< std::int32_t, 4, Arch >	maskz_dpbusds (predicate< 4, Arch > maskmask, simd< std::int32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Evaluate maskz_dpbusds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnni)) \|\| (!Arch.has(x86_feature::avxvnni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int16_t, 8, Arch>); })
consteval simd< std::int32_t, 4, Arch >	dpwssd (simd< std::int32_t, 4, Arch > accumulator, simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	Evaluate dpwssd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int16_t, 8, Arch>); })
consteval simd< std::int32_t, 4, Arch >	mask_dpwssd (simd< std::int32_t, 4, Arch > accumulator, predicate< 4, Arch > maskmask, simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	Evaluate mask_dpwssd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int16_t, 8, Arch>); })
consteval simd< std::int32_t, 4, Arch >	maskz_dpwssd (predicate< 4, Arch > maskmask, simd< std::int32_t, 4, Arch > accumulator, simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	Evaluate maskz_dpwssd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnni)) \|\| (!Arch.has(x86_feature::avxvnni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int16_t, 8, Arch>); })
consteval simd< std::int32_t, 4, Arch >	dpwssds (simd< std::int32_t, 4, Arch > accumulator, simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	Evaluate dpwssds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int16_t, 8, Arch>); })
consteval simd< std::int32_t, 4, Arch >	mask_dpwssds (simd< std::int32_t, 4, Arch > accumulator, predicate< 4, Arch > maskmask, simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	Evaluate mask_dpwssds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int16_t, 8, Arch>); })
consteval simd< std::int32_t, 4, Arch >	maskz_dpwssds (predicate< 4, Arch > maskmask, simd< std::int32_t, 4, Arch > accumulator, simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	Evaluate maskz_dpwssds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnni)) \|\| (!Arch.has(x86_feature::avxvnni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::uint8_t, 32, Arch> ); sizeof(simd<std::int8_t, 32, Arch>); })
consteval simd< std::int32_t, 8, Arch >	dpbusd (simd< std::int32_t, 8, Arch > accumulator, simd< std::uint8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	Evaluate dpbusd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::int8_t, 32, Arch>); })
consteval simd< std::int32_t, 8, Arch >	mask_dpbusd (simd< std::int32_t, 8, Arch > accumulator, predicate< 8, Arch > maskmask, simd< std::uint8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	Evaluate mask_dpbusd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::int8_t, 32, Arch>); })
consteval simd< std::int32_t, 8, Arch >	maskz_dpbusd (predicate< 8, Arch > maskmask, simd< std::int32_t, 8, Arch > accumulator, simd< std::uint8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	Evaluate maskz_dpbusd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnni)) \|\| (!Arch.has(x86_feature::avxvnni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::uint8_t, 32, Arch> ); sizeof(simd<std::int8_t, 32, Arch>); })
consteval simd< std::int32_t, 8, Arch >	dpbusds (simd< std::int32_t, 8, Arch > accumulator, simd< std::uint8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	Evaluate dpbusds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::int8_t, 32, Arch>); })
consteval simd< std::int32_t, 8, Arch >	mask_dpbusds (simd< std::int32_t, 8, Arch > accumulator, predicate< 8, Arch > maskmask, simd< std::uint8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	Evaluate mask_dpbusds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::int8_t, 32, Arch>); })
consteval simd< std::int32_t, 8, Arch >	maskz_dpbusds (predicate< 8, Arch > maskmask, simd< std::int32_t, 8, Arch > accumulator, simd< std::uint8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	Evaluate maskz_dpbusds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnni)) \|\| (!Arch.has(x86_feature::avxvnni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::int16_t, 16, Arch>); })
consteval simd< std::int32_t, 8, Arch >	dpwssd (simd< std::int32_t, 8, Arch > accumulator, simd< std::int16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	Evaluate dpwssd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::int16_t, 16, Arch>); })
consteval simd< std::int32_t, 8, Arch >	mask_dpwssd (simd< std::int32_t, 8, Arch > accumulator, predicate< 8, Arch > maskmask, simd< std::int16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	Evaluate mask_dpwssd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::int16_t, 16, Arch>); })
consteval simd< std::int32_t, 8, Arch >	maskz_dpwssd (predicate< 8, Arch > maskmask, simd< std::int32_t, 8, Arch > accumulator, simd< std::int16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	Evaluate maskz_dpwssd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnni)) \|\| (!Arch.has(x86_feature::avxvnni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::int16_t, 16, Arch>); })
consteval simd< std::int32_t, 8, Arch >	dpwssds (simd< std::int32_t, 8, Arch > accumulator, simd< std::int16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	Evaluate dpwssds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::int16_t, 16, Arch>); })
consteval simd< std::int32_t, 8, Arch >	mask_dpwssds (simd< std::int32_t, 8, Arch > accumulator, predicate< 8, Arch > maskmask, simd< std::int16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	Evaluate mask_dpwssds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::int16_t, 16, Arch>); })
consteval simd< std::int32_t, 8, Arch >	maskz_dpwssds (predicate< 8, Arch > maskmask, simd< std::int32_t, 8, Arch > accumulator, simd< std::int16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	Evaluate maskz_dpwssds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))) && requires { sizeof(simd<std::int32_t, 16, Arch>); sizeof(simd<std::uint8_t, 64, Arch>); sizeof(simd<std::int8_t, 64, Arch>); })
consteval simd< std::int32_t, 16, Arch >	dpbusd (simd< std::int32_t, 16, Arch > accumulator, simd< std::uint8_t, 64, Arch > a, simd< std::int8_t, 64, Arch > b) noexcept
	Evaluate dpbusd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))) && requires { sizeof(simd<std::int32_t, 16, Arch>); sizeof(simd<std::uint8_t, 64, Arch>); sizeof(simd<std::int8_t, 64, Arch>); })
consteval simd< std::int32_t, 16, Arch >	mask_dpbusd (simd< std::int32_t, 16, Arch > accumulator, predicate< 16, Arch > maskmask, simd< std::uint8_t, 64, Arch > a, simd< std::int8_t, 64, Arch > b) noexcept
	Evaluate mask_dpbusd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))) && requires { sizeof(simd<std::int32_t, 16, Arch>); sizeof(simd<std::uint8_t, 64, Arch>); sizeof(simd<std::int8_t, 64, Arch>); })
consteval simd< std::int32_t, 16, Arch >	maskz_dpbusd (predicate< 16, Arch > maskmask, simd< std::int32_t, 16, Arch > accumulator, simd< std::uint8_t, 64, Arch > a, simd< std::int8_t, 64, Arch > b) noexcept
	Evaluate maskz_dpbusd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))) && requires { sizeof(simd<std::int32_t, 16, Arch>); sizeof(simd<std::uint8_t, 64, Arch>); sizeof(simd<std::int8_t, 64, Arch>); })
consteval simd< std::int32_t, 16, Arch >	dpbusds (simd< std::int32_t, 16, Arch > accumulator, simd< std::uint8_t, 64, Arch > a, simd< std::int8_t, 64, Arch > b) noexcept
	Evaluate dpbusds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))) && requires { sizeof(simd<std::int32_t, 16, Arch>); sizeof(simd<std::uint8_t, 64, Arch>); sizeof(simd<std::int8_t, 64, Arch>); })
consteval simd< std::int32_t, 16, Arch >	mask_dpbusds (simd< std::int32_t, 16, Arch > accumulator, predicate< 16, Arch > maskmask, simd< std::uint8_t, 64, Arch > a, simd< std::int8_t, 64, Arch > b) noexcept
	Evaluate mask_dpbusds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))) && requires { sizeof(simd<std::int32_t, 16, Arch>); sizeof(simd<std::uint8_t, 64, Arch>); sizeof(simd<std::int8_t, 64, Arch>); })
consteval simd< std::int32_t, 16, Arch >	maskz_dpbusds (predicate< 16, Arch > maskmask, simd< std::int32_t, 16, Arch > accumulator, simd< std::uint8_t, 64, Arch > a, simd< std::int8_t, 64, Arch > b) noexcept
	Evaluate maskz_dpbusds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))) && requires { sizeof(simd<std::int32_t, 16, Arch>); sizeof(simd<std::int16_t, 32, Arch>); })
consteval simd< std::int32_t, 16, Arch >	dpwssd (simd< std::int32_t, 16, Arch > accumulator, simd< std::int16_t, 32, Arch > a, simd< std::int16_t, 32, Arch > b) noexcept
	Evaluate dpwssd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))) && requires { sizeof(simd<std::int32_t, 16, Arch>); sizeof(simd<std::int16_t, 32, Arch>); })
consteval simd< std::int32_t, 16, Arch >	mask_dpwssd (simd< std::int32_t, 16, Arch > accumulator, predicate< 16, Arch > maskmask, simd< std::int16_t, 32, Arch > a, simd< std::int16_t, 32, Arch > b) noexcept
	Evaluate mask_dpwssd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))) && requires { sizeof(simd<std::int32_t, 16, Arch>); sizeof(simd<std::int16_t, 32, Arch>); })
consteval simd< std::int32_t, 16, Arch >	maskz_dpwssd (predicate< 16, Arch > maskmask, simd< std::int32_t, 16, Arch > accumulator, simd< std::int16_t, 32, Arch > a, simd< std::int16_t, 32, Arch > b) noexcept
	Evaluate maskz_dpwssd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))) && requires { sizeof(simd<std::int32_t, 16, Arch>); sizeof(simd<std::int16_t, 32, Arch>); })
consteval simd< std::int32_t, 16, Arch >	dpwssds (simd< std::int32_t, 16, Arch > accumulator, simd< std::int16_t, 32, Arch > a, simd< std::int16_t, 32, Arch > b) noexcept
	Evaluate dpwssds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))) && requires { sizeof(simd<std::int32_t, 16, Arch>); sizeof(simd<std::int16_t, 32, Arch>); })
consteval simd< std::int32_t, 16, Arch >	mask_dpwssds (simd< std::int32_t, 16, Arch > accumulator, predicate< 16, Arch > maskmask, simd< std::int16_t, 32, Arch > a, simd< std::int16_t, 32, Arch > b) noexcept
	Evaluate mask_dpwssds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vnni))) && requires { sizeof(simd<std::int32_t, 16, Arch>); sizeof(simd<std::int16_t, 32, Arch>); })
consteval simd< std::int32_t, 16, Arch >	maskz_dpwssds (predicate< 16, Arch > maskmask, simd< std::int32_t, 16, Arch > accumulator, simd< std::int16_t, 32, Arch > a, simd< std::int16_t, 32, Arch > b) noexcept
	Evaluate maskz_dpwssds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint8))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int8_t, 16, Arch>); })
consteval simd< std::int32_t, 4, Arch >	dpbssd (simd< std::int32_t, 4, Arch > accumulator, simd< std::int8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Evaluate dpbssd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint8))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::int8_t, 32, Arch>); })
consteval simd< std::int32_t, 8, Arch >	dpbssd (simd< std::int32_t, 8, Arch > accumulator, simd< std::int8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	Evaluate dpbssd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint8))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int8_t, 16, Arch>); })
consteval simd< std::int32_t, 4, Arch >	dpbssds (simd< std::int32_t, 4, Arch > accumulator, simd< std::int8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
	Evaluate dpbssds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint8))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::int8_t, 32, Arch>); })
consteval simd< std::int32_t, 8, Arch >	dpbssds (simd< std::int32_t, 8, Arch > accumulator, simd< std::int8_t, 32, Arch > a, simd< std::int8_t, 32, Arch > b) noexcept
	Evaluate dpbssds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint8))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int8_t, 16, Arch>); sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::int32_t, 4, Arch >	dpbsud (simd< std::int32_t, 4, Arch > accumulator, simd< std::int8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate dpbsud at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint8))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::int8_t, 32, Arch>); sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::int32_t, 8, Arch >	dpbsud (simd< std::int32_t, 8, Arch > accumulator, simd< std::int8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Evaluate dpbsud at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint8))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int8_t, 16, Arch>); sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::int32_t, 4, Arch >	dpbsuds (simd< std::int32_t, 4, Arch > accumulator, simd< std::int8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate dpbsuds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint8))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::int8_t, 32, Arch>); sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::int32_t, 8, Arch >	dpbsuds (simd< std::int32_t, 8, Arch > accumulator, simd< std::int8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Evaluate dpbsuds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint8))) && requires { sizeof(simd<std::uint32_t, 4, Arch>); sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	dpbuud (simd< std::uint32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate dpbuud at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint8))) && requires { sizeof(simd<std::uint32_t, 8, Arch>); sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	dpbuud (simd< std::uint32_t, 8, Arch > accumulator, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Evaluate dpbuud at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint8))) && requires { sizeof(simd<std::uint32_t, 4, Arch>); sizeof(simd<std::uint8_t, 16, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	dpbuuds (simd< std::uint32_t, 4, Arch > accumulator, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
	Evaluate dpbuuds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint8))) && requires { sizeof(simd<std::uint32_t, 8, Arch>); sizeof(simd<std::uint8_t, 32, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	dpbuuds (simd< std::uint32_t, 8, Arch > accumulator, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept
	Evaluate dpbuuds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint16))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int16_t, 8, Arch>); sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::int32_t, 4, Arch >	dpwsud (simd< std::int32_t, 4, Arch > accumulator, simd< std::int16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Evaluate dpwsud at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint16))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::int16_t, 16, Arch>); sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::int32_t, 8, Arch >	dpwsud (simd< std::int32_t, 8, Arch > accumulator, simd< std::int16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Evaluate dpwsud at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint16))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::int16_t, 8, Arch>); sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::int32_t, 4, Arch >	dpwsuds (simd< std::int32_t, 4, Arch > accumulator, simd< std::int16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Evaluate dpwsuds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint16))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::int16_t, 16, Arch>); sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::int32_t, 8, Arch >	dpwsuds (simd< std::int32_t, 8, Arch > accumulator, simd< std::int16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Evaluate dpwsuds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint16))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::uint16_t, 8, Arch>); sizeof(simd<std::int16_t, 8, Arch>); })
consteval simd< std::int32_t, 4, Arch >	dpwusd (simd< std::int32_t, 4, Arch > accumulator, simd< std::uint16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	Evaluate dpwusd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint16))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::uint16_t, 16, Arch>); sizeof(simd<std::int16_t, 16, Arch>); })
consteval simd< std::int32_t, 8, Arch >	dpwusd (simd< std::int32_t, 8, Arch > accumulator, simd< std::uint16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	Evaluate dpwusd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint16))) && requires { sizeof(simd<std::int32_t, 4, Arch>); sizeof(simd<std::uint16_t, 8, Arch>); sizeof(simd<std::int16_t, 8, Arch>); })
consteval simd< std::int32_t, 4, Arch >	dpwusds (simd< std::int32_t, 4, Arch > accumulator, simd< std::uint16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b) noexcept
	Evaluate dpwusds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint16))) && requires { sizeof(simd<std::int32_t, 8, Arch>); sizeof(simd<std::uint16_t, 16, Arch>); sizeof(simd<std::int16_t, 16, Arch>); })
consteval simd< std::int32_t, 8, Arch >	dpwusds (simd< std::int32_t, 8, Arch > accumulator, simd< std::uint16_t, 16, Arch > a, simd< std::int16_t, 16, Arch > b) noexcept
	Evaluate dpwusds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint16))) && requires { sizeof(simd<std::uint32_t, 4, Arch>); sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	dpwuud (simd< std::uint32_t, 4, Arch > accumulator, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Evaluate dpwuud at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint16))) && requires { sizeof(simd<std::uint32_t, 8, Arch>); sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	dpwuud (simd< std::uint32_t, 8, Arch > accumulator, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Evaluate dpwuud at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint16))) && requires { sizeof(simd<std::uint32_t, 4, Arch>); sizeof(simd<std::uint16_t, 8, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	dpwuuds (simd< std::uint32_t, 4, Arch > accumulator, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Evaluate dpwuuds at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avxvnniint16))) && requires { sizeof(simd<std::uint32_t, 8, Arch>); sizeof(simd<std::uint16_t, 16, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	dpwuuds (simd< std::uint32_t, 8, Arch > accumulator, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Evaluate dpwuuds at compile time when its register storage is available.
template<isa< x86 > Arch, class... Args>
void	dpbusd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	mask_dpbusd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	maskz_dpbusd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	dpbusds (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	mask_dpbusds (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	maskz_dpbusds (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	dpwssd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	mask_dpwssd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	maskz_dpwssd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	dpwssds (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	mask_dpwssds (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	maskz_dpwssds (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	dpbssd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	dpbssds (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	dpbsud (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	dpbsuds (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	dpbuud (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	dpbuuds (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	dpwsud (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	dpwsuds (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	dpwusd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	dpwusds (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	dpwuud (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	dpwuuds (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::pclmul) && Arch.has(x86_feature::avx) && Imm8 <= 255)
constexpr simd< std::uint64_t, 2, Arch >	vpclmulqdq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Multiply selected halves of one 128-bit lane using PCLMUL and AVX.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::vpclmulqdq) && Arch.has(x86_feature::avx) && Imm8 <= 255)
constexpr simd< std::uint64_t, 4, Arch >	vpclmulqdq (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Multiply selected halves independently in two 128-bit lanes; AVX suffices.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::vpclmulqdq) && Arch.has(x86_feature::avx512f) && Imm8 <= 255)
constexpr simd< std::uint64_t, 8, Arch >	vpclmulqdq (simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Multiply selected halves independently in four 128-bit lanes; needs AVX512F.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::pclmul) && Arch.has(x86_feature::avx))) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	vpclmulqdq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Evaluate vpclmulqdq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::vpclmulqdq) && Arch.has(x86_feature::avx))) && Imm8 <= 255 && requires { sizeof(simd <std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	vpclmulqdq (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Evaluate vpclmulqdq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::vpclmulqdq) && Arch.has(x86_feature::avx512f))) && Imm8 <= 255 && requires { sizeof(simd <std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	vpclmulqdq (simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Evaluate vpclmulqdq at compile time when its register storage is available.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	vpclmulqdq (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq))
constexpr simd< std::uint32_t, 16, Arch >	vpopcntd (simd< std::uint32_t, 16, Arch > value) noexcept
	Count set bits in each of the 16 32-bit lanes; results are in [0, 32].
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq))
constexpr simd< std::uint32_t, 16, Arch >	mask_vpopcntd (simd< std::uint32_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > value) noexcept
	Inactive lanes retain source; mask bits above the lane count are ignored.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq))
constexpr simd< std::uint32_t, 16, Arch >	maskz_vpopcntd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > value) noexcept
	Inactive lanes become zero; mask bits above the lane count are ignored.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq))
constexpr simd< std::uint64_t, 8, Arch >	vpopcntq (simd< std::uint64_t, 8, Arch > value) noexcept
	Count set bits in each of the 8 64-bit lanes; results are in [0, 64].
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq))
constexpr simd< std::uint64_t, 8, Arch >	mask_vpopcntq (simd< std::uint64_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > value) noexcept
	Inactive lanes retain source; mask bits above the lane count are ignored.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq))
constexpr simd< std::uint64_t, 8, Arch >	maskz_vpopcntq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > value) noexcept
	Inactive lanes become zero; mask bits above the lane count are ignored.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	vpopcntd (simd< std::uint32_t, 4, Arch > value) noexcept
	Count set bits in each of the 4 32-bit lanes; results are in [0, 32].
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	mask_vpopcntd (simd< std::uint32_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > value) noexcept
	Inactive lanes retain source; mask bits above the lane count are ignored.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	maskz_vpopcntd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > value) noexcept
	Inactive lanes become zero; mask bits above the lane count are ignored.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	vpopcntq (simd< std::uint64_t, 2, Arch > value) noexcept
	Count set bits in each of the 2 64-bit lanes; results are in [0, 64].
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	mask_vpopcntq (simd< std::uint64_t, 2, Arch > source, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > value) noexcept
	Inactive lanes retain source; mask bits above the lane count are ignored.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	maskz_vpopcntq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > value) noexcept
	Inactive lanes become zero; mask bits above the lane count are ignored.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	vpopcntd (simd< std::uint32_t, 8, Arch > value) noexcept
	Count set bits in each of the 8 32-bit lanes; results are in [0, 32].
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	mask_vpopcntd (simd< std::uint32_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > value) noexcept
	Inactive lanes retain source; mask bits above the lane count are ignored.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	maskz_vpopcntd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > value) noexcept
	Inactive lanes become zero; mask bits above the lane count are ignored.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	vpopcntq (simd< std::uint64_t, 4, Arch > value) noexcept
	Count set bits in each of the 4 64-bit lanes; results are in [0, 64].
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	mask_vpopcntq (simd< std::uint64_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > value) noexcept
	Inactive lanes retain source; mask bits above the lane count are ignored.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	maskz_vpopcntq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > value) noexcept
	Inactive lanes become zero; mask bits above the lane count are ignored.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq))) && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	vpopcntd (simd< std::uint32_t, 16, Arch > value) noexcept
	Evaluate vpopcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq))) && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	mask_vpopcntd (simd< std::uint32_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > value) noexcept
	Evaluate mask_vpopcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq))) && requires { sizeof(simd<std::uint32_t, 16, Arch>); })
consteval simd< std::uint32_t, 16, Arch >	maskz_vpopcntd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > value) noexcept
	Evaluate maskz_vpopcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq))) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	vpopcntq (simd< std::uint64_t, 8, Arch > value) noexcept
	Evaluate vpopcntq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq))) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	mask_vpopcntq (simd< std::uint64_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > value) noexcept
	Evaluate mask_vpopcntq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq))) && requires { sizeof(simd<std::uint64_t, 8, Arch>); })
consteval simd< std::uint64_t, 8, Arch >	maskz_vpopcntq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > value) noexcept
	Evaluate maskz_vpopcntq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	vpopcntd (simd< std::uint32_t, 4, Arch > value) noexcept
	Evaluate vpopcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	mask_vpopcntd (simd< std::uint32_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > value) noexcept
	Evaluate mask_vpopcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch >	maskz_vpopcntd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > value) noexcept
	Evaluate maskz_vpopcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	vpopcntq (simd< std::uint64_t, 2, Arch > value) noexcept
	Evaluate vpopcntq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	mask_vpopcntq (simd< std::uint64_t, 2, Arch > source, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > value) noexcept
	Evaluate mask_vpopcntq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
consteval simd< std::uint64_t, 2, Arch >	maskz_vpopcntq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > value) noexcept
	Evaluate maskz_vpopcntq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	vpopcntd (simd< std::uint32_t, 8, Arch > value) noexcept
	Evaluate vpopcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	mask_vpopcntd (simd< std::uint32_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > value) noexcept
	Evaluate mask_vpopcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint32_t, 8, Arch>); })
consteval simd< std::uint32_t, 8, Arch >	maskz_vpopcntd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > value) noexcept
	Evaluate maskz_vpopcntd at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	vpopcntq (simd< std::uint64_t, 4, Arch > value) noexcept
	Evaluate vpopcntq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	mask_vpopcntq (simd< std::uint64_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > value) noexcept
	Evaluate mask_vpopcntq at compile time when its register storage is available.
template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512vpopcntdq) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint64_t, 4, Arch>); })
consteval simd< std::uint64_t, 4, Arch >	maskz_vpopcntq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > value) noexcept
	Evaluate maskz_vpopcntq at compile time when its register storage is available.
template<isa< x86 > Arch, class... Args>
void	vpopcntd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	mask_vpopcntd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	maskz_vpopcntd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	vpopcntq (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	mask_vpopcntq (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	maskz_vpopcntq (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<waiter W>
void	wait_until (volatile auto *p, auto f) noexcept(noexcept(!f(p)) &&noexcept(W::monitor(p)) &&noexcept(W::mwait(0))) native_blocking
	Wait until a predicate holds about a given memory location.
template<isa< x86 > Arch = NATIVE_BASELINE, unsigned Control = 1> requires (Arch.has(x86_feature::waitpkg) && Control < 2)
std::uint8_t	tpause (std::uint64_t deadline) noexcept native_blocking
auto	with_waiter (auto k) noexcept(noexcept(k.template operator()<mwaitx >()) &&noexcept(k.template operator()<umwait >()) &&noexcept(k.template operator()<spin >()))
	finds an appropriate waiter for the current CPU Prefer MWAITX, then WAITPKG, otherwise PAUSE. Invoke k once with that type. Runtime detection occurs here, not in a SIMD arithmetic operation. Usage:
template<isa< arm > Arch> requires (Arch.has(arm_feature::crc))
constexpr std::uint32_t	crc32 (std::uint32_t accumulator, std::uint8_t value) noexcept
	Update the CRC32 accumulator with exactly 8 input bits.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::crc))
consteval std::uint32_t	crc32 (std::uint32_t accumulator, std::uint8_t value) noexcept
	Evaluate the 8-bit CRC32 update at compile time without requiring CRC instructions.
template<isa< arm > Arch> requires (Arch.has(arm_feature::crc))
constexpr std::uint32_t	crc32 (std::uint32_t accumulator, std::uint16_t value) noexcept
	Update the CRC32 accumulator with exactly 16 input bits.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::crc))
consteval std::uint32_t	crc32 (std::uint32_t accumulator, std::uint16_t value) noexcept
	Evaluate the 16-bit CRC32 update at compile time without requiring CRC instructions.
template<isa< arm > Arch> requires (Arch.has(arm_feature::crc))
constexpr std::uint32_t	crc32 (std::uint32_t accumulator, std::uint32_t value) noexcept
	Update the CRC32 accumulator with exactly 32 input bits.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::crc))
consteval std::uint32_t	crc32 (std::uint32_t accumulator, std::uint32_t value) noexcept
	Evaluate the 32-bit CRC32 update at compile time without requiring CRC instructions.
template<isa< arm > Arch> requires (Arch.has(arm_feature::crc))
constexpr std::uint32_t	crc32 (std::uint32_t accumulator, std::uint64_t value) noexcept
	Update the CRC32 accumulator with exactly 64 input bits.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::crc))
consteval std::uint32_t	crc32 (std::uint32_t accumulator, std::uint64_t value) noexcept
	Evaluate the 64-bit CRC32 update at compile time without requiring CRC instructions.
template<isa< arm > Arch, class A, class B>
void	crc32 (A, B)=delete
	Reject implicit narrowing or conversion to a different operand width.
template<isa< arm > Arch> requires (Arch.has(arm_feature::crc))
constexpr std::uint32_t	crc32c (std::uint32_t accumulator, std::uint8_t value) noexcept
	Update the CRC32C accumulator with exactly 8 input bits.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::crc))
consteval std::uint32_t	crc32c (std::uint32_t accumulator, std::uint8_t value) noexcept
	Evaluate the 8-bit CRC32C update at compile time without requiring CRC instructions.
template<isa< arm > Arch> requires (Arch.has(arm_feature::crc))
constexpr std::uint32_t	crc32c (std::uint32_t accumulator, std::uint16_t value) noexcept
	Update the CRC32C accumulator with exactly 16 input bits.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::crc))
consteval std::uint32_t	crc32c (std::uint32_t accumulator, std::uint16_t value) noexcept
	Evaluate the 16-bit CRC32C update at compile time without requiring CRC instructions.
template<isa< arm > Arch> requires (Arch.has(arm_feature::crc))
constexpr std::uint32_t	crc32c (std::uint32_t accumulator, std::uint32_t value) noexcept
	Update the CRC32C accumulator with exactly 32 input bits.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::crc))
consteval std::uint32_t	crc32c (std::uint32_t accumulator, std::uint32_t value) noexcept
	Evaluate the 32-bit CRC32C update at compile time without requiring CRC instructions.
template<isa< arm > Arch> requires (Arch.has(arm_feature::crc))
constexpr std::uint32_t	crc32c (std::uint32_t accumulator, std::uint64_t value) noexcept
	Update the CRC32C accumulator with exactly 64 input bits.
template<isa< arm > Arch> requires (!Arch.has(arm_feature::crc))
consteval std::uint32_t	crc32c (std::uint32_t accumulator, std::uint64_t value) noexcept
	Evaluate the 64-bit CRC32C update at compile time without requiring CRC instructions.
template<isa< arm > Arch, class A, class B>
void	crc32c (A, B)=delete
	Reject implicit narrowing or conversion to a different operand width.
template<simd_integer_element To, simd_integer_element From, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (sizeof(From) * N % sizeof(To) == 0 && requires { typename simd<From,N,Arch>::native_type; typename simd<To,sizeof(From)N/sizeof(To),Arch>::native_type; } && sizeof(typename simd<From,N,Arch>::native_type) == sizeof(typename simd<To,sizeof(From)N/sizeof(To),Arch>::native_type) && (sizeof(typename simd<From,N,Arch> ::native_type) <= 16 \|\| sizeof(typename simd<From,N,Arch>::native_type) == 32 \|\| sizeof(typename simd<From,N,Arch> ::native_type) == 64 ))
constexpr auto	reinterpret_bits (simd< From, N, Arch > value) noexcept -> simd< To, sizeof(From) *N/sizeof(To), Arch >
template<simd_integer_element T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (std::is_unsigned_v<T> && sizeof(T) <= 4 && N > 1 && N % 2 == 0 && detail::integer_arithmetic<T,N,Arch>)
constexpr auto	pairwise_add_widened (simd< T, N, Arch > value) noexcept
template<simd_integer_element T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (std::is_unsigned_v<T> && detail::integer_arithmetic<T,N,Arch>)
constexpr simd< T, N, Arch >	popcount (simd< T, N, Arch > value) noexcept
template<simd_integer_element T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (std::is_unsigned_v<T> && sizeof(T)<=4 && detail::integer_arithmetic<T,N,Arch>)
constexpr std::uint64_t	reduce_add_widened (simd< T, N, Arch > value) noexcept
template<simd_integer_element To, simd_integer_element From, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (std::is_unsigned_v<To> && std::is_unsigned_v<From> && sizeof(From) == 2 * sizeof(To) && // The selected backend must implement this width. Complete storage alone // does not establish the arithmetic instructions used by this operation. (N * sizeof(From) == 16 \|\| N * sizeof(From) == 32 \|\| (N * sizeof(From) == 64 && (sizeof(From) >= 4 \|\| 1 != 0)) ) && requires { sizeof(simd<From, N, Arch>); sizeof(simd<To, 2 * N, Arch>); })
constexpr simd< To, 2 *N, Arch >	narrow_concat (simd< From, N, Arch > a, simd< From, N, Arch > b) noexcept
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator+ (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator- (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator* (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator/ (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator% (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator& (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator\| (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator^ (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator<< (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator>> (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator== (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator!= (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator< (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator<= (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator> (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator>= (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator+= (simd< T, N, A > &, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator-= (simd< T, N, A > &, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator*= (simd< T, N, A > &, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator/= (simd< T, N, A > &, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator%= (simd< T, N, A > &, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator&= (simd< T, N, A > &, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator\|= (simd< T, N, A > &, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator^= (simd< T, N, A > &, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator<<= (simd< T, N, A > &, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator>>= (simd< T, N, A > &, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class V, class U, std::size_t A = 1, simd_access Access = simd_access::ordinary> requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) && requires(U const * p) { V::template load_memory<A>(p); }
constexpr V	load_simd (U const *p, simd_memory< A, Access >={}) noexcept(noexcept(V::template load_memory< A >(p)))
template<class V, simd_custom_element U, std::size_t A = 1, simd_access Access = simd_access::ordinary> requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) && std::same_as <typename V::value_type,typename simd_traits<U>::storage_type>
constexpr V	load_simd (U const *p, simd_memory< A, Access >={}) noexcept(noexcept(V::template rebind< U >::template load_memory< A >(p).to_native()))
template<class U, class V, std::size_t A = 1, simd_access Access = simd_access::ordinary> requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) && requires(V value,U * p) { value.template store_memory<A>(p); }
constexpr void	store_simd (U *p, V value, simd_memory< A, Access >={}) noexcept(noexcept(value.template store_memory< A >(p)))
template<simd_custom_element U, class V, std::size_t A = 1, simd_access Access = simd_access::ordinary> requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) && std::same_as <typename V::value_type,typename simd_traits<U>::storage_type>
constexpr void	store_simd (U *p, V value, simd_memory< A, Access >={}) noexcept(noexcept(typename V::template rebind< U >(value).template store_memory< A >(p)))
template<class V, class U, std::size_t N> requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) &&(N==V::lanes) && requires(U const * p) { ::native::load_simd<V>(p); }
constexpr V	load_simd (std::array< U, N > const &values) noexcept(noexcept(::native::load_simd< V >(values.data())))
template<class V, class U, std::size_t N> requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) &&(N==V::lanes) && requires(U * p) { ::native::load_simd<V>(p); }
constexpr V	load_simd (std::span< U, N > values) noexcept(noexcept(::native::load_simd< V >(values.data())))
template<class V, class U, std::size_t A = 1, simd_access Access = simd_access::ordinary> requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) && std::default_initializable<U> && std::constructible_from<U,typename V::value_type &> && std::is_copy_assignable_v<U> && requires(U const * p) { ::native::load_simd<V>(p); }
constexpr V	load_simd_partial (U const *p, std::size_t count, typename V::value_type fill={}, simd_memory< A, Access >={}) noexcept(std::is_nothrow_default_constructible_v< U > &&std::is_nothrow_constructible_v< U, typename V::value_type & > &&std::is_nothrow_copy_assignable_v< U > &&noexcept(::native::load_simd< V >(p)))
template<class U, class V, std::size_t A = 1, simd_access Access = simd_access::ordinary> requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) && std::default_initializable<U> && std::is_copy_assignable_v<U> && requires(U * p,V value) { ::native::store_simd(p,value); }
constexpr void	store_simd_partial (U *p, V value, std::size_t count, simd_memory< A, Access >={}) noexcept(std::is_nothrow_default_constructible_v< U > &&std::is_nothrow_copy_assignable_v< U > &&noexcept(::native::store_simd(p, value)))
template<bool Flush = false, std::size_t L, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<L>
constexpr simd< float, L, Arch >	exp2 (simd< float, L, Arch > input) noexcept
template<bool Flush = false, std::size_t L, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<L>
constexpr std::array< simd< float, L, Arch >, N >	exp2 (std::array< simd< float, L, Arch >, N > const &input) noexcept
template<bool Flush, std::size_t L, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<L>
constexpr simd< float, L, Arch >	exp2 (simd< float, L, Arch > input, std::bool_constant< Flush >) noexcept
template<bool Flush, std::size_t L, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<L>
constexpr std::array< simd< float, L, Arch >, N >	exp2 (std::array< simd< float, L, Arch >, N > const &input, std::bool_constant< Flush >) noexcept
template<std::size_t L, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<L>
constexpr simd< float, L, Arch >	atan2 (simd< float, L, Arch > y, simd< float, L, Arch > x) noexcept
template<std::size_t L, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<L>
constexpr std::array< simd< float, L, Arch >, N >	atan2 (std::array< simd< float, L, Arch >, N > const &y, std::array< simd< float, L, Arch >, N > const &x) noexcept
template<bool Flush = false, unsigned Degree = 6, std::size_t L, ::native::isa<> Arch> requires (Degree >= 1 && Degree <= 7) && (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<L>
constexpr simd< float, L, Arch >	exp (simd< float, L, Arch > input) noexcept
	Evaluate the binary32 range-reduced exponential approximation. Degree selects a polynomial from one through seven, defaulting to six. Every degree shares range reduction and exponent scaling; none promises correctly rounded exp for every input. Flush selects the early underflow cutoff at compile time; it does not change CPU controls or turn a raw vector into a policy-bearing FTZ type.
template<bool Flush = false, unsigned Degree = 6, std::size_t L, std::size_t N, ::native::isa<> Arch> requires (Degree >= 1 && Degree <= 7) && (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<L>
constexpr std::array< simd< float, L, Arch >, N >	exp (std::array< simd< float, L, Arch >, N > const &input) noexcept
template<bool Flush, unsigned Degree = 6, std::size_t L, std::size_t N, ::native::isa<> Arch> requires (Degree >= 1 && Degree <= 7) && (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<L>
constexpr std::array< simd< float, L, Arch >, N >	exp (std::array< simd< float, L, Arch >, N > const &input, std::bool_constant< Flush >, std::integral_constant< unsigned, Degree >={}) noexcept
template<bool Flush, unsigned Degree = 6, std::size_t L, ::native::isa<> Arch> requires (Degree >= 1 && Degree <= 7) && (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<L>
constexpr simd< float, L, Arch >	exp (simd< float, L, Arch > input, std::bool_constant< Flush >, std::integral_constant< unsigned, Degree >={}) noexcept
template<class U, class T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && simd_mask_element<U> && simd_mask_element<T> && requires { typename simd<U,N,Arch> ::native_type; typename simd<T,N,Arch>::native_type; }
constexpr simd< U, N, Arch >	mask_cast (simd< T, N, Arch > value) noexcept
template<class T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && simd_mask_element<T> && ::native::detail::avx512_backend::predicate_shape<N> && requires { typename simd<T,N,Arch>::native_type; }
constexpr predicate< N, Arch >	to_predicate (simd< T, N, Arch > value) noexcept
template<class T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && simd_mask_element<T> && ::native::detail::avx512_backend::predicate_shape<N> && requires { typename simd<T,N,Arch>::native_type; }
constexpr simd< T, N, Arch >	to_vector_mask (predicate< N, Arch > value) noexcept
template<std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && requires { typename simd<bool,N,Arch>::native_type; }
constexpr simd< mask8, N, Arch >	to_vector_mask (simd< bool, N, Arch > value) noexcept
	Expand lane truth into canonical zero/all-one full-vector mask lanes.
template<class T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && simd_mask_element<T> && requires { typename simd<bool,N,Arch>::native_type; typename simd <T,N,Arch>::native_type; }
constexpr simd< bool, N, Arch >	to_bool (simd< T, N, Arch > value) noexcept
	Convert lane truth into Boolean data lanes represented as zero or one, preserving the lane count.
template<std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::predicate_shape<N> && requires { typename simd<bool,N, Arch>::native_type; }
constexpr simd< bool, N, Arch >	to_bool (predicate< N, Arch > value) noexcept
	Convert lane truth into Boolean data lanes represented as zero or one, preserving the lane count.
template<std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::predicate_shape<N> && requires { typename simd<bool,N, Arch>::native_type; }
constexpr predicate< N, Arch >	to_predicate (simd< bool, N, Arch > value) noexcept
	Compress lane truth into the supported compact predicate representation.
template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> && ::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)
constexpr simd< T, N, Arch >	select (M m, simd< T, N, Arch > a, simd< T, N, Arch > b)
template<simd_integer_element T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::integer_shape<T, N>
constexpr simd< T, N, Arch >	bit_select (simd< T, N, Arch > bits, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
template<simd_integer_element T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::integer_shape<T, N>
constexpr simd< T, N, Arch >	select (simd< T, N, Arch > bits, simd< T, N, Arch > a, simd< T, N, Arch > b)
template<simd_mask_element M, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch )
constexpr auto	mask_bits (simd< M, N, Arch > m) noexcept
template<simd_integer_element T, simd_mask_element M, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) &&(sizeof(T) == sizeof(M))
constexpr simd< std::make_unsigned_t< T >, N, Arch >	mask_bits (simd< M, N, Arch > m) noexcept
template<simd_integer_element T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && requires(predicate<N,Arch> m) { to_vector_mask <::native::detail::avx512_backend::mask_lane_for<T>>(m); }
constexpr simd< std::make_unsigned_t< T >, N, Arch >	mask_bits (predicate< N, Arch > m) noexcept
template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> && ::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)
constexpr simd< T, N, Arch >	masked_add (M m, simd< T, N, Arch > prior, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> && ::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)
constexpr simd< T, N, Arch >	masked_add_zero (M m, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> && ::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)
constexpr simd< T, N, Arch >	masked_sub (M m, simd< T, N, Arch > prior, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> && ::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)
constexpr simd< T, N, Arch >	masked_sub_zero (M m, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> && ::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)
constexpr simd< T, N, Arch >	masked_mul (M m, simd< T, N, Arch > prior, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> && ::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)
constexpr simd< T, N, Arch >	masked_mul_zero (M m, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
template<simd_integer_element T, std::size_t N, std::size_t K, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (K >= sizeof(T) * 8)
void	operator<< (simd< T, N, Arch > a, imm_t< K >)
	Reject this unsupported operand combination instead of converting implicitly to a native register.
template<simd_integer_element T, std::size_t N, std::size_t K, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (K >= sizeof(T) * 8)
void	operator>> (simd< T, N, Arch > a, imm_t< K >)
	Reject this unsupported operand combination instead of converting implicitly to a native register.
template<std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::native_scaleb_shape<N> &&(std::same_as<M,typename simd <float,N,Arch>::mask_type> \|\| std::same_as<M,typename simd<float,N,Arch>::vector_mask_type>)
constexpr simd< float, N, Arch >	masked_scaleb (M maskmask, simd< float, N, Arch > prior, simd< float, N, Arch > value, simd< float, N, Arch > exponent) noexcept
template<std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::native_scaleb_shape<N> &&(std::same_as<M,typename simd <float,N,Arch>::mask_type> \|\| std::same_as<M,typename simd<float,N,Arch>::vector_mask_type>)
constexpr simd< float, N, Arch >	masked_scaleb_zero (M maskmask, simd< float, N, Arch > value, simd< float, N, Arch > exponent) noexcept
template<std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::native_scaleb_shape<N>
constexpr simd< float, N, Arch >	scaleb (simd< float, N, Arch > value, simd< float, N, Arch > exponent) noexcept
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator+ (simd< float, N, Arch > a, U b) noexcept(noexcept(simd< float, N, Arch >(b)))
	Add corresponding floating-point lanes using the caller's rounding and denormal environment.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator+ (U a, simd< float, N, Arch > b) noexcept(noexcept(simd< float, N, Arch >(a)))
	Add corresponding floating-point lanes using the caller's rounding and denormal environment.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator- (simd< float, N, Arch > a, U b) noexcept(noexcept(simd< float, N, Arch >(b)))
	Subtract corresponding floating-point lanes using the caller's rounding and denormal environment.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator- (U a, simd< float, N, Arch > b) noexcept(noexcept(simd< float, N, Arch >(a)))
	Subtract corresponding floating-point lanes using the caller's rounding and denormal environment.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator* (simd< float, N, Arch > a, U b) noexcept(noexcept(simd< float, N, Arch >(b)))
	Multiply corresponding floating-point lanes using the caller's rounding and denormal environment.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator* (U a, simd< float, N, Arch > b) noexcept(noexcept(simd< float, N, Arch >(a)))
	Multiply corresponding floating-point lanes using the caller's rounding and denormal environment.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator/ (simd< float, N, Arch > a, U b) noexcept(noexcept(simd< float, N, Arch >(b)))
	Divide corresponding floating-point lanes using the caller's rounding and denormal environment.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator/ (U a, simd< float, N, Arch > b) noexcept(noexcept(simd< float, N, Arch >(a)))
	Divide corresponding floating-point lanes using the caller's rounding and denormal environment.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator< (simd< float, N, Arch > a, U b) noexcept(noexcept(simd< float, N, Arch >(b)))
	Return a mask whose lanes are true where a < b holds. NaN lanes yield false.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator< (U a, simd< float, N, Arch > b) noexcept(noexcept(simd< float, N, Arch >(a)))
	Return a mask whose lanes are true where a < b holds. NaN lanes yield false.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator> (simd< float, N, Arch > a, U b) noexcept(noexcept(simd< float, N, Arch >(b)))
	Return a mask whose lanes are true where a > b holds. NaN lanes yield false.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator> (U a, simd< float, N, Arch > b) noexcept(noexcept(simd< float, N, Arch >(a)))
	Return a mask whose lanes are true where a > b holds. NaN lanes yield false.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator<= (simd< float, N, Arch > a, U b) noexcept(noexcept(simd< float, N, Arch >(b)))
	Return a mask whose lanes are true where a <= b holds. NaN lanes yield false.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator<= (U a, simd< float, N, Arch > b) noexcept(noexcept(simd< float, N, Arch >(a)))
	Return a mask whose lanes are true where a <= b holds. NaN lanes yield false.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator>= (simd< float, N, Arch > a, U b) noexcept(noexcept(simd< float, N, Arch >(b)))
	Return a mask whose lanes are true where a >= b holds. NaN lanes yield false.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator>= (U a, simd< float, N, Arch > b) noexcept(noexcept(simd< float, N, Arch >(a)))
	Return a mask whose lanes are true where a >= b holds. NaN lanes yield false.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator== (simd< float, N, Arch > a, U b) noexcept(noexcept(simd< float, N, Arch >(b)))
	Return a mask whose lanes are true where a == b holds. NaN lanes yield false.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator== (U a, simd< float, N, Arch > b) noexcept(noexcept(simd< float, N, Arch >(a)))
	Return a mask whose lanes are true where a == b holds. NaN lanes yield false.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator!= (simd< float, N, Arch > a, U b) noexcept(noexcept(simd< float, N, Arch >(b)))
	Return a mask whose lanes are true where a != b holds. NaN lanes compare unequal.
template<std::size_t N, class U, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<U>) && (!std::same_as<U,simd<float,N,Arch>>) && std::convertible_to <U,simd<float,N,Arch>>
constexpr auto	operator!= (U a, simd< float, N, Arch > b) noexcept(noexcept(simd< float, N, Arch >(a)))
	Return a mask whose lanes are true where a != b holds. NaN lanes compare unequal.
template<std::size_t N, class A, class B, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<A> && !::native::detail::avx512_backend::custom_argument<B>) && std::convertible_to<A,simd<float,N,Arch>> && std::convertible_to<B,simd<float,N,Arch>>
constexpr auto	fma (simd< float, N, Arch > a, A b, B c) noexcept(noexcept(simd< float, N, Arch >(b)) &&noexcept(simd< float, N, Arch >(c)))
	Compute a*b+c with one fused rounding per logical lane in the caller's floating-point environment.
template<std::size_t N, class A, class B, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<A> && !::native::detail::avx512_backend::custom_argument<B>) && (!std::same_as<A,simd<float,N,Arch>>) && std::convertible_to<A,simd<float,N,Arch>> && std::convertible_to<B,simd<float, N,Arch>>
constexpr auto	fma (A a, simd< float, N, Arch > b, B c) noexcept(noexcept(simd< float, N, Arch >(a)) &&noexcept(simd< float, N, Arch >(c)))
	Compute a*b+c with one fused rounding per logical lane in the caller's floating-point environment.
template<std::size_t N, class A, class B, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && (!::native::detail::avx512_backend::custom_argument<A> && !::native::detail::avx512_backend::custom_argument<B>) && (!std::same_as<A,simd<float,N,Arch>>) && (!std::same_as<B,simd<float,N,Arch>>) && std::convertible_to<A,simd<float,N, Arch>> && std::convertible_to<B,simd<float,N,Arch>>
constexpr auto	fma (A a, B b, simd< float, N, Arch > c) noexcept(noexcept(simd< float, N, Arch >(a)) &&noexcept(simd< float, N, Arch >(b)))
	Compute a*b+c with one fused rounding per logical lane in the caller's floating-point environment.
template<std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N>
constexpr auto	abs (simd< float, N, Arch > a) noexcept
template<class To, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && std::same_as<To,std::int32_t>
constexpr simd< To, N, Arch >	convert (simd< float, N, Arch > x) noexcept
template<class To, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && std::same_as<To,float>
constexpr simd< To, N, Arch >	convert (simd< std::int32_t, N, Arch > x) noexcept
template<simd_integer_element T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) &&(N==2 \|\| N==3) && (sizeof(T)==4)
constexpr simd< T, N, Arch >	bit_select (simd< T, N, Arch > bits, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Choose each bit from a where the corresponding mask bit is one, otherwise from b; arbitrary bit masks are permitted.
template<simd_integer_element T, std::size_t N, ::native::isa<> Arch, class M> requires (::native::avx512 <= Arch ) &&(N==2 \|\| N==3) && (sizeof(T)==4) && (std::same_as<M,typename simd<T,N,Arch>::mask> \|\| std::same_as<M,simd<mask32,N,Arch>>)
constexpr simd< T, N, Arch >	masked_add (M m, simd< T, N, Arch > prior, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Add matching integer lanes, retaining prior in inactive mask lanes; arithmetic wraps at the lane width.
template<simd_integer_element T, std::size_t N, ::native::isa<> Arch, class M> requires (::native::avx512 <= Arch ) &&(N==2 \|\| N==3) && (sizeof(T)==4) && (std::same_as<M,typename simd<T,N,Arch>::mask> \|\| std::same_as<M,simd<mask32,N,Arch>>)
constexpr simd< T, N, Arch >	masked_sub (M m, simd< T, N, Arch > prior, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Subtract matching integer lanes, retaining prior in inactive mask lanes; arithmetic wraps at the lane width.
template<simd_integer_element T, std::size_t N, ::native::isa<> Arch, class M> requires (::native::avx512 <= Arch ) &&(N==2 \|\| N==3) && (sizeof(T)==4) && (std::same_as<M,typename simd<T,N,Arch>::mask> \|\| std::same_as<M,simd<mask32,N,Arch>>)
constexpr simd< T, N, Arch >	masked_mul (M m, simd< T, N, Arch > prior, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Multiply matching integer lanes, retaining prior in inactive mask lanes; arithmetic wraps at the lane width.
template<std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N>
constexpr simd< float, N, Arch >	floor (simd< float, N, Arch > x) noexcept
template<std::size_t N, std::size_t M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N>
constexpr std::array< simd< float, N, Arch >, M >	floor (std::array< simd< float, N, Arch >, M > const &input) noexcept
template<std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N>
constexpr simd< float, N, Arch >	ceil (simd< float, N, Arch > x) noexcept
template<std::size_t N, std::size_t M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N>
constexpr std::array< simd< float, N, Arch >, M >	ceil (std::array< simd< float, N, Arch >, M > const &input) noexcept
template<std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N>
constexpr simd< float, N, Arch >	trunc (simd< float, N, Arch > x) noexcept
template<std::size_t N, std::size_t M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N>
constexpr std::array< simd< float, N, Arch >, M >	trunc (std::array< simd< float, N, Arch >, M > const &input) noexcept
template<class T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (std::same_as<T,float> \|\| std::same_as<T,std::int32_t> \|\| std::same_as<T,std::uint32_t>) && ::native::detail::avx512_backend::float_shape<N>
constexpr compaction_result< simd< T, N, Arch > >	compress (typename simd< T, N, Arch >::mask maskmask, simd< T, N, Arch > value, T fill=T{}) noexcept
template<class T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (std::same_as<T,float> \|\| std::same_as<T,std::int32_t> \|\| std::same_as<T,std::uint32_t>) && ::native::detail::avx512_backend::float_shape<N>
constexpr simd< T, N, Arch >	expand (typename simd< T, N, Arch >::mask maskmask, simd< T, N, Arch > packed, simd< T, N, Arch > prior) noexcept
template<class T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (std::same_as<T,float> \|\| std::same_as<T,std::int32_t> \|\| std::same_as<T,std::uint32_t>) && ::native::detail::avx512_backend::float_shape<N>
constexpr std::size_t	compress_store (T *destination, std::size_t capacity, typename simd< T, N, Arch >::mask maskmask, simd< T, N, Arch > value) noexcept
template<detail::wasm_number T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16)
constexpr simd< T, N, A >	select (typename simd< T, N, A >::mask_type m, simd< T, N, A > a, simd< T, N, A > b) noexcept
	Select full lanes from a where m is true, otherwise from b.
template<detail::wasm_number T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16)
constexpr simd< T, N, A >	bit_select (simd< detail::wasm_word< T >, N, A > m, simd< T, N, A > a, simd< T, N, A > b) noexcept
	Select individual representation bits using the unsigned mask words.
template<class To, class U, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(U) * N == 16) && (sizeof(To) == sizeof(U)) && simd_integer_element<To>
constexpr simd< To, N, A >	mask_bits (simd< mask_lane< U >, N, A > m) noexcept
	Reinterpret canonical mask lanes as corresponding integer words.
template<std::size_t I, detail::wasm_number T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16) && (I < N)
constexpr simd< T, N, A >	broadcast (simd< T, N, A > v, imm_t< I >) noexcept
	Broadcast one compile-time-selected lane.
template<std::size_t... I, detail::wasm_number T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16) && (sizeof...(I) == N) && ((I < 2 * N) && ...)
constexpr simd< T, N, A >	shuffle (simd< T, N, A > a, simd< T, N, A > b) noexcept
	Select N lanes from the concatenation of two inputs, using constant indices.
template<isa<> A> requires (A.has(wasm_feature::simd128))
constexpr simd< std::uint8_t, 16, A >	swizzle (simd< std::uint8_t, 16, A > v, simd< std::uint8_t, 16, A > indices) noexcept
	Look up byte indices 0..15; every other index produces zero.
template<std::floating_point T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16)
constexpr simd< T, N, A >	sqrt (simd< T, N, A > v) noexcept
	Compute correctly rounded square roots; negative finite lanes produce NaN.
template<std::floating_point T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16)
constexpr simd< T, N, A >	floor (simd< T, N, A > v) noexcept
	Round floating lanes toward negative infinity.
template<std::floating_point T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16)
constexpr simd< T, N, A >	ceil (simd< T, N, A > v) noexcept
	Round floating lanes toward positive infinity.
template<std::floating_point T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16)
constexpr simd< T, N, A >	trunc (simd< T, N, A > v) noexcept
	Round floating lanes toward zero.
template<std::floating_point T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16)
constexpr simd< T, N, A >	round_even (simd< T, N, A > v) noexcept
	Round floating lanes to nearest integers, choosing even at ties.
template<std::floating_point T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16)
constexpr simd< T, N, A >	abs (simd< T, N, A > v) noexcept
	Clear the floating sign bit without changing payload bits.
template<simd_integer_element T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16 && sizeof(T) <= 2)
constexpr simd< T, N, A >	add_sat (simd< T, N, A > a, simd< T, N, A > b) noexcept
	Saturate signed or unsigned byte/halfword arithmetic at the lane limits.
template<simd_integer_element T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16 && sizeof(T) <= 2)
constexpr simd< T, N, A >	sub_sat (simd< T, N, A > a, simd< T, N, A > b) noexcept
	Saturate signed or unsigned byte/halfword arithmetic at the lane limits.
template<simd_integer_element T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (std::is_unsigned_v<T> && sizeof(T) * N == 16 && sizeof(T) <= 2)
constexpr simd< T, N, A >	average_round (simd< T, N, A > a, simd< T, N, A > b) noexcept
	Rounded unsigned average: (a+b+1)/2 without intermediate overflow.
template<simd_integer_element T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (std::is_signed_v<T> && sizeof(T) * N == 16)
constexpr simd< T, N, A >	abs (simd< T, N, A > a) noexcept
	Absolute value with the minimum signed lane retaining its representation.
template<detail::wasm_number T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16)
constexpr simd< T, N, A >	min (simd< T, N, A > a, simd< T, N, A > b) noexcept
	Minimum/maximum; floating NaNs propagate and signed zeros follow WebAssembly rules.
template<detail::wasm_number T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16)
constexpr simd< T, N, A >	max (simd< T, N, A > a, simd< T, N, A > b) noexcept
	Minimum/maximum; floating NaNs propagate and signed zeros follow WebAssembly rules.
template<detail::wasm_number T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16 && std::is_floating_point_v<T>)
constexpr simd< T, N, A >	pmin (simd< T, N, A > a, simd< T, N, A > b) noexcept
	Pseudo minimum/maximum selects the first operand for unordered or equal lanes.
template<detail::wasm_number T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16 && std::is_floating_point_v<T>)
constexpr simd< T, N, A >	pmax (simd< T, N, A > a, simd< T, N, A > b) noexcept
	Pseudo minimum/maximum selects the first operand for unordered or equal lanes.
template<simd_integer_element T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16 && sizeof(T) <= 4)
constexpr auto	extend_low (simd< T, N, A > a) noexcept
	Widen the lower half of integer lanes, preserving signedness.
template<simd_integer_element T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16 && sizeof(T) <= 4)
constexpr auto	multiply_widened_low (simd< T, N, A > a, simd< T, N, A > b) noexcept
	Multiply widened lower integer lanes; the complete product fits.
template<simd_integer_element T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16 && sizeof(T) <= 4)
constexpr auto	extend_high (simd< T, N, A > a) noexcept
	Widen the upper half of integer lanes, preserving signedness.
template<simd_integer_element T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16 && sizeof(T) <= 4)
constexpr auto	multiply_widened_high (simd< T, N, A > a, simd< T, N, A > b) noexcept
	Multiply widened upper integer lanes; the complete product fits.
template<simd_integer_element To, simd_integer_element From, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(From) * N == 16 && sizeof(From) == 2 * sizeof(To) && sizeof(To) <= 2 && std::is_signed_v<From>)
constexpr simd< To, N *2, A >	narrow_sat (simd< From, N, A > a, simd< From, N, A > b) noexcept
	Saturating concatenate from signed source lanes, including unsigned destinations.
template<isa<> A> requires (A.has(wasm_feature::simd128))
constexpr simd< std::int16_t, 8, A >	q15mulr_sat (simd< std::int16_t, 8, A > a, simd< std::int16_t, 8, A > b) noexcept
	Multiply signed Q15 lanes, round by adding 2^14, shift by 15 and saturate.
template<isa<> A> requires (A.has(wasm_feature::simd128))
constexpr simd< std::int32_t, 4, A >	dot (simd< std::int16_t, 8, A > a, simd< std::int16_t, 8, A > b) noexcept
	Sum adjacent signed halfword products modulo 2^32.
template<simd_integer_element To, std::floating_point From, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(From) * N == 16 && sizeof(To) == 4)
constexpr simd< To, 4, A >	trunc_sat (simd< From, N, A > a) noexcept
template<std::floating_point To, detail::wasm_number From, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(From) * N == 16 && (sizeof(From) == 4 \|\| std::is_floating_point_v<From>) && !std::same_as<To, From>)
constexpr simd< To, 16/sizeof(To), A >	convert (simd< From, N, A > a) noexcept
template<class V> requires detail::wasm_number<typename V::value_type> && (V::architecture.has(wasm_feature::simd128)) && (V::lanes * sizeof(typename V::value_type) == 16)
constexpr V	load_splat (typename V::value_type const *p) noexcept
	Read one scalar and broadcast it; the access is exactly sizeof(T) bytes.
template<std::size_t I, detail::wasm_number T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16 && I < N)
constexpr simd< T, N, A >	load_lane (T const *p, simd< T, N, A > a) noexcept
	Read one scalar into lane I, preserving the other lanes.
template<std::size_t I, detail::wasm_number T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16 && I < N)
constexpr void	store_lane (T *p, simd< T, N, A > a) noexcept
	Write only lane I to one scalar object.
template<class V> requires (V::architecture.has(wasm_feature::simd128)) && (V::lanes * sizeof(typename V::value_type) == 16 && sizeof(typename V::value_type) >= 4)
constexpr V	load_zero (typename V::value_type const *p) noexcept
	Read one 32- or 64-bit lane and zero the other lanes.
template<simd_integer_element To, simd_integer_element From, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(To) == 2 * sizeof(From) && std::is_signed_v<To> == std::is_signed_v<From>)
constexpr simd< To, 16/sizeof(To), A >	load_widened (From const *p) noexcept
	Read exactly eight bytes of source lanes and widen them with their signedness.
template<simd_integer_element T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (std::is_signed_v<T> && sizeof(T) * N == 16 && sizeof(T) <= 2)
constexpr auto	pairwise_add_widened (simd< T, N, A > a) noexcept
	Signed widening pairwise sums; unsigned overloads are shared with the integer API.
template<simd_integer_element T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16)
constexpr std::uint32_t	bitmask (simd< T, N, A > a) noexcept
	Gather each integer lane's sign bit into bit i of the scalar result.
template<simd_integer_element T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16)
constexpr bool	any (simd< T, N, A > a) noexcept
	Test whether at least one integer lane is nonzero.
template<simd_integer_element T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16)
constexpr bool	all (simd< T, N, A > a) noexcept
	Test whether every integer lane is nonzero.
constexpr std::span< std::uint8_t const >	wasm_feature_probe (wasm_feature feature) noexcept
constexpr wasm_capabilities	decode_wasm_capabilities (wasm_capabilities::raw_observations raw) noexcept
template<class V> requires requires(V & validate,std::span<std::uint8_t const> bytes) { { validate(bytes) } noexcept -> std::same_as<std::optional <bool>>; }
constexpr wasm_capabilities	observe_wasm_capabilities (V &&validate) noexcept
constexpr wasm_capabilities	observe_wasm_capabilities () noexcept
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::bmi2) && Imm8 <= 255)
constexpr std::uint32_t	rorx (std::uint32_t value) noexcept
	Rotate right by an immediate byte; the low five bits select the 32-bit rotation.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::bmi2) && Imm8 <= 255)
constexpr std::uint64_t	rorx (std::uint64_t value) noexcept
	Rotate right by an immediate byte; the low six bits select the 64-bit rotation.
template<isa< x86 > Arch, unsigned Imm8> requires (!Arch.has(x86_feature::bmi2) && Imm8 <= 255)
consteval std::uint32_t	rorx (std::uint32_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch, unsigned Imm8> requires (!Arch.has(x86_feature::bmi2) && Imm8 <= 255)
consteval std::uint64_t	rorx (std::uint64_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::crc32))
constexpr std::uint32_t	crc32c (std::uint32_t accumulator, std::uint64_t value) noexcept
template<isa< x86 > Arch> requires (!Arch.has(x86_feature::crc32))
consteval std::uint32_t	crc32c (std::uint32_t accumulator, std::uint64_t value) noexcept
	Evaluate the same operation at compile time when Arch lacks the feature.
template<detail::instruction_feature E>
	isa (E) -> isa< detail::family_of< E > >
	Deduce the family from a feature enum; explicit isa<> always names the host family.
template<arch A, arch B> requires detail::same_arch<A,B>
constexpr auto	operator& (A left, B right) noexcept
	Requirements compose by union within one family; both operands are required.
constexpr bool	operator< (x86_feature, x86_feature) noexcept
	A singleton feature is never a strict subset of another singleton.
constexpr bool	operator> (x86_feature, x86_feature) noexcept
	A singleton feature is never a strict superset of another singleton.
constexpr bool	operator<= (x86_feature a, x86_feature b) noexcept
	Singleton inclusion holds exactly when both feature names are equal.
constexpr bool	operator>= (x86_feature a, x86_feature b) noexcept
	Reverse singleton inclusion holds exactly when both features are equal.
constexpr bool	operator< (arm_feature, arm_feature) noexcept
	A singleton feature is never a strict subset of another singleton.
constexpr bool	operator> (arm_feature, arm_feature) noexcept
	A singleton feature is never a strict superset of another singleton.
constexpr bool	operator<= (arm_feature a, arm_feature b) noexcept
	Singleton inclusion holds exactly when both feature names are equal.
constexpr bool	operator>= (arm_feature a, arm_feature b) noexcept
	Reverse singleton inclusion holds exactly when both features are equal.
constexpr bool	operator< (wasm_feature, wasm_feature) noexcept
	A singleton feature is never a strict subset of another singleton.
constexpr bool	operator> (wasm_feature, wasm_feature) noexcept
	A singleton feature is never a strict superset of another singleton.
constexpr bool	operator<= (wasm_feature a, wasm_feature b) noexcept
	Singleton inclusion holds exactly when both feature names are equal.
constexpr bool	operator>= (wasm_feature a, wasm_feature b) noexcept
	Reverse singleton inclusion holds exactly when both features are equal.
template<arch A, arch B> requires detail::same_arch<A,B>
constexpr bool	operator<= (A a, B b) noexcept
	True when every feature required by a is present in b of the same family.
template<arch A, arch B> requires detail::same_arch<A,B>
constexpr bool	operator>= (A a, B b) noexcept
	True when a contains every feature required by b of the same family.
template<arch A, arch B> requires detail::same_arch<A,B>
constexpr bool	operator< (A a, B b) noexcept
	True when a is a proper subset of b within the same family.
template<arch A, arch B> requires detail::same_arch<A,B>
constexpr bool	operator> (A a, B b) noexcept
	True when a strictly contains b within the same family.
template<arch A>
constexpr auto	feature_closure (A input) noexcept
template<architecture Family = target_arch>
constexpr isa< Family >	target_features (std::string_view text) noexcept
template<class C> requires detail::normalized_features<C,x86> && requires(C const & c) { c.xcr0; c.xcr0_observed; }
constexpr isa_admission< x86 >	classify_isa (C const &cpu, isa< x86 > requested, isa< x86 > minimum={}) noexcept
template<class C> requires detail::normalized_features<C,arm>
constexpr isa_admission< arm >	classify_isa (C const &cpu, isa< arm > requested, isa< arm > minimum={}) noexcept
template<class C> requires detail::normalized_features<C,wasm>
constexpr isa_admission< wasm >	classify_isa (C const &runtime, isa< wasm > requested, isa< wasm > minimum={}) noexcept
template<detail::x86_observation C> requires (!detail::has_feature_observation<C>) && requires(C const & c) { c.xcr0; c.xcr0_observed; }
constexpr isa_admission< x86 >	classify_isa (C const &cpu, isa< x86 > requested, isa< x86 > minimum={}) noexcept
template<detail::arm_observation C> requires (!detail::has_feature_observation<C>)
constexpr isa_admission< arm >	classify_isa (C const &cpu, isa< arm > requested, isa< arm > minimum={}) noexcept
template<architecture Family>
	target_entry (isa< Family >, isa< Family >={}) -> target_entry< Family >
	Deduce a source record from same-family ISA values.
template<detail::instruction_feature E>
	target_entry (E) -> target_entry< detail::family_of< E > >
	Deduce a source record from a feature enum.
template<arch A, arch B> requires detail::same_arch<A,B>
	target_entry (A, B) -> target_entry< detail::arch_family_v< A > >
	Deduce a source record from same-family feature and ISA operands.
template<auto... A, auto... B>
constexpr isa_list< A..., B... >	operator+ (isa_list< A... >, isa_list< B... >) noexcept
	Concatenate ordered source metadata without sorting or deduplicating it.
template<auto... Entries, detail::capability_observation C, class F> requires ((decltype(detail::abi_match<Entries,0>::architecture)::family==detail::observation_family<C>) && ...)
constexpr bool	with_isa (isa_list< Entries... >, C const &cpu, F &&callback, isa< detail::observation_family< C > > minimum={})
	Admit the first available source variant and invoke callback.operator()().
template<class T, class... U> requires (std::same_as<T,U> && ...)
	wide (T, U...) -> wide< T, 1+sizeof...(U)>
	Deduce the common element type and the number of homogeneous constructor arguments.
template<class A, class B> requires detail::wide_generic_detail::wide_arguments<A, B> && (::native::detail::wide_target<A,B> == NATIVE_WIDE_INDEX) && requires(detail::wide_generic_detail::wide_element_t<A> const & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a + b; }
constexpr auto	operator+ (A const &a, B const &b) noexcept(noexcept(detail::wide_generic_detail::wide_dispatch(a, b, detail::wide_generic_detail::wide_add{})))
template<class A, class B> requires detail::wide_generic_detail::wide_arguments<A, B> && (::native::detail::wide_target<A,B> == NATIVE_WIDE_INDEX) && requires(detail::wide_generic_detail::wide_element_t<A> const & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a - b; }
constexpr auto	operator- (A const &a, B const &b) noexcept(noexcept(detail::wide_generic_detail::wide_dispatch(a, b, detail::wide_generic_detail::wide_sub{})))
template<class A, class B> requires detail::wide_generic_detail::wide_arguments<A, B> && (::native::detail::wide_target<A,B> == NATIVE_WIDE_INDEX) && requires(detail::wide_generic_detail::wide_element_t<A> const & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a * b; }
constexpr auto	operator* (A const &a, B const &b) noexcept(noexcept(detail::wide_generic_detail::wide_dispatch(a, b, detail::wide_generic_detail::wide_mul{})))
template<class A, class B> requires detail::wide_generic_detail::wide_arguments<A, B> && (::native::detail::wide_target<A,B> == NATIVE_WIDE_INDEX) && requires(detail::wide_generic_detail::wide_element_t<A> const & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a / b; }
constexpr auto	operator/ (A const &a, B const &b)
template<class A, class B> requires detail::wide_generic_detail::wide_arguments<A, B> && (::native::detail::wide_target<A,B> == NATIVE_WIDE_INDEX) && requires(detail::wide_generic_detail::wide_element_t<A> const & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a % b; }
constexpr auto	operator% (A const &a, B const &b)
template<class A, class B> requires detail::wide_generic_detail::wide_arguments<A, B> && (::native::detail::wide_target<A,B> == NATIVE_WIDE_INDEX) && requires(detail::wide_generic_detail::wide_element_t<A> const & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a & b; }
constexpr auto	operator& (A const &a, B const &b)
template<class A, class B> requires detail::wide_generic_detail::wide_arguments<A, B> && (::native::detail::wide_target<A,B> == NATIVE_WIDE_INDEX) && requires(detail::wide_generic_detail::wide_element_t<A> const & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a \| b; }
constexpr auto	operator\| (A const &a, B const &b)
template<class A, class B> requires detail::wide_generic_detail::wide_arguments<A, B> && (::native::detail::wide_target<A,B> == NATIVE_WIDE_INDEX) && requires(detail::wide_generic_detail::wide_element_t<A> const & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a ^ b; }
constexpr auto	operator^ (A const &a, B const &b)
template<class A, class B> requires detail::wide_generic_detail::wide_arguments<A, B> && (::native::detail::wide_target<A,B> == NATIVE_WIDE_INDEX) && requires(detail::wide_generic_detail::wide_element_t<A> const & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a << b; }
constexpr auto	operator<< (A const &a, B const &b)
template<class A, class B> requires detail::wide_generic_detail::wide_arguments<A, B> && (::native::detail::wide_target<A,B> == NATIVE_WIDE_INDEX) && requires(detail::wide_generic_detail::wide_element_t<A> const & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a >> b; }
constexpr auto	operator>> (A const &a, B const &b)
template<class A, class B> requires detail::wide_generic_detail::wide_arguments<A, B> && (::native::detail::wide_target<A,B> == NATIVE_WIDE_INDEX) && requires(detail::wide_generic_detail::wide_element_t<A> const & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a == b; }
constexpr auto	operator== (A const &a, B const &b)
template<class A, class B> requires detail::wide_generic_detail::wide_arguments<A, B> && (::native::detail::wide_target<A,B> == NATIVE_WIDE_INDEX) && requires(detail::wide_generic_detail::wide_element_t<A> const & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a != b; }
constexpr auto	operator!= (A const &a, B const &b)
template<class A, class B> requires detail::wide_generic_detail::wide_arguments<A, B> && (::native::detail::wide_target<A,B> == NATIVE_WIDE_INDEX) && requires(detail::wide_generic_detail::wide_element_t<A> const & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a < b; }
constexpr auto	operator< (A const &a, B const &b)
template<class A, class B> requires detail::wide_generic_detail::wide_arguments<A, B> && (::native::detail::wide_target<A,B> == NATIVE_WIDE_INDEX) && requires(detail::wide_generic_detail::wide_element_t<A> const & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a > b; }
constexpr auto	operator> (A const &a, B const &b)
template<class A, class B> requires detail::wide_generic_detail::wide_arguments<A, B> && (::native::detail::wide_target<A,B> == NATIVE_WIDE_INDEX) && requires(detail::wide_generic_detail::wide_element_t<A> const & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a <= b; }
constexpr auto	operator<= (A const &a, B const &b)
template<class A, class B> requires detail::wide_generic_detail::wide_arguments<A, B> && (::native::detail::wide_target<A,B> == NATIVE_WIDE_INDEX) && requires(detail::wide_generic_detail::wide_element_t<A> const & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a >= b; }
constexpr auto	operator>= (A const &a, B const &b)
template<class T, std::size_t N> requires (::native::detail::wide_target<T> == NATIVE_WIDE_INDEX) && requires(T const & a) { +a; }
constexpr auto	operator+ (wide< T, N > const &a)
template<class T, std::size_t N> requires (::native::detail::wide_target<T> == NATIVE_WIDE_INDEX) && requires(T const & a) { -a; }
constexpr auto	operator- (wide< T, N > const &a)
template<class T, std::size_t N> requires (::native::detail::wide_target<T> == NATIVE_WIDE_INDEX) && requires(T const & a) { ~a; }
constexpr auto	operator~ (wide< T, N > const &a)
template<class T, std::size_t N> requires (::native::detail::wide_target<T> == NATIVE_WIDE_INDEX) && requires(T const & a) { !a; }
constexpr auto	operator! (wide< T, N > const &a)
template<class T, std::size_t N, class B> requires (::native::detail::wide_target<T,B> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_arguments<wide<T, N>, B> && (detail::wide_generic_detail::wide_batch_assignable<wide<T,N>,B,detail::wide_generic_detail::wide_add> \|\| ((detail::wide_generic_detail::wide_traits<B>::value \|\| std::copy_constructible<B>) && requires(T & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a += b; }))
constexpr wide< T, N > &	operator+= (wide< T, N > &a, B const &b) noexcept([] { if constexpr(detail::wide_generic_detail::wide_batch_assignable< wide< T, N >, B, detail::wide_generic_detail::wide_add >) return noexcept(std::declval< wide< T, N > & >()=detail::wide_generic_detail::wide_dispatch(std::declval< wide< T, N > const & >(), std::declval< B const & >(), detail::wide_generic_detail::wide_add{}));else return false;}())
template<class T, std::size_t N, class B> requires (::native::detail::wide_target<T,B> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_arguments<wide<T, N>, B> && (detail::wide_generic_detail::wide_batch_assignable<wide<T,N>,B,detail::wide_generic_detail::wide_sub> \|\| ((detail::wide_generic_detail::wide_traits<B>::value \|\| std::copy_constructible<B>) && requires(T & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a -= b; }))
constexpr wide< T, N > &	operator-= (wide< T, N > &a, B const &b) noexcept([] { if constexpr(detail::wide_generic_detail::wide_batch_assignable< wide< T, N >, B, detail::wide_generic_detail::wide_sub >) return noexcept(std::declval< wide< T, N > & >()=detail::wide_generic_detail::wide_dispatch(std::declval< wide< T, N > const & >(), std::declval< B const & >(), detail::wide_generic_detail::wide_sub{}));else return false;}())
template<class T, std::size_t N, class B> requires (::native::detail::wide_target<T,B> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_arguments<wide<T, N>, B> && (detail::wide_generic_detail::wide_batch_assignable<wide<T,N>,B,detail::wide_generic_detail::wide_mul> \|\| ((detail::wide_generic_detail::wide_traits<B>::value \|\| std::copy_constructible<B>) && requires(T & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a *= b; }))
constexpr wide< T, N > &	operator*= (wide< T, N > &a, B const &b) noexcept([] { if constexpr(detail::wide_generic_detail::wide_batch_assignable< wide< T, N >, B, detail::wide_generic_detail::wide_mul >) return noexcept(std::declval< wide< T, N > & >()=detail::wide_generic_detail::wide_dispatch(std::declval< wide< T, N > const & >(), std::declval< B const & >(), detail::wide_generic_detail::wide_mul{}));else return false;}())
template<class T, std::size_t N, class B> requires (::native::detail::wide_target<T,B> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_arguments<wide<T, N>, B> && (detail::wide_generic_detail::wide_traits<B>::value \|\| std::copy_constructible<B>) && requires(T & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a /= b; }
constexpr wide< T, N > &	operator/= (wide< T, N > &a, B const &b)
template<class T, std::size_t N, class B> requires (::native::detail::wide_target<T,B> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_arguments<wide<T, N>, B> && (detail::wide_generic_detail::wide_traits<B>::value \|\| std::copy_constructible<B>) && requires(T & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a %= b; }
constexpr wide< T, N > &	operator%= (wide< T, N > &a, B const &b)
template<class T, std::size_t N, class B> requires (::native::detail::wide_target<T,B> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_arguments<wide<T, N>, B> && (detail::wide_generic_detail::wide_traits<B>::value \|\| std::copy_constructible<B>) && requires(T & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a &= b; }
constexpr wide< T, N > &	operator&= (wide< T, N > &a, B const &b)
template<class T, std::size_t N, class B> requires (::native::detail::wide_target<T,B> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_arguments<wide<T, N>, B> && (detail::wide_generic_detail::wide_traits<B>::value \|\| std::copy_constructible<B>) && requires(T & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a \|= b; }
constexpr wide< T, N > &	operator\|= (wide< T, N > &a, B const &b)
template<class T, std::size_t N, class B> requires (::native::detail::wide_target<T,B> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_arguments<wide<T, N>, B> && (detail::wide_generic_detail::wide_traits<B>::value \|\| std::copy_constructible<B>) && requires(T & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a ^= b; }
constexpr wide< T, N > &	operator^= (wide< T, N > &a, B const &b)
template<class T, std::size_t N, class B> requires (::native::detail::wide_target<T,B> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_arguments<wide<T, N>, B> && (detail::wide_generic_detail::wide_traits<B>::value \|\| std::copy_constructible<B>) && requires(T & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a <<= b; }
constexpr wide< T, N > &	operator<<= (wide< T, N > &a, B const &b)
template<class T, std::size_t N, class B> requires (::native::detail::wide_target<T,B> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_arguments<wide<T, N>, B> && (detail::wide_generic_detail::wide_traits<B>::value \|\| std::copy_constructible<B>) && requires(T & a, detail::wide_generic_detail::wide_element_t<B> const & b) { a >>= b; }
constexpr wide< T, N > &	operator>>= (wide< T, N > &a, B const &b)
template<class T, std::size_t N> requires (::native::detail::wide_target<T> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_value_operation<N, detail::wide_generic_detail::wide_isfinite,T>
constexpr auto	isfinite (wide< T, N > const &input) noexcept(noexcept(detail::wide_generic_detail::wide_map< detail::wide_generic_detail::wide_isfinite >(input)))
template<class T, std::size_t N> requires (::native::detail::wide_target<T> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_value_operation<N, detail::wide_generic_detail::wide_isinf,T>
constexpr auto	isinf (wide< T, N > const &input) noexcept(noexcept(detail::wide_generic_detail::wide_map< detail::wide_generic_detail::wide_isinf >(input)))
template<class T, std::size_t N> requires (::native::detail::wide_target<T> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_value_operation<N, detail::wide_generic_detail::wide_isnan,T>
constexpr auto	isnan (wide< T, N > const &input) noexcept(noexcept(detail::wide_generic_detail::wide_map< detail::wide_generic_detail::wide_isnan >(input)))
template<class T, std::size_t N> requires (::native::detail::wide_target<T> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_value_operation<N, detail::wide_generic_detail::wide_signbit,T>
constexpr auto	signbit (wide< T, N > const &input) noexcept(noexcept(detail::wide_generic_detail::wide_map< detail::wide_generic_detail::wide_signbit >(input)))
template<class T, std::size_t N> requires (::native::detail::wide_target<T> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_value_operation<N, detail::wide_generic_detail::wide_copysign,T,T> && std::same_as<detail::wide_generic_detail::wide_result <detail::wide_generic_detail::wide_copysign,T,T>,T>
constexpr wide< T, N >	copysign (wide< T, N > const &a, wide< T, N > const &b) noexcept(noexcept(detail::wide_generic_detail::wide_map< detail::wide_generic_detail::wide_copysign >(a, b)))
template<class T, std::size_t N> requires (::native::detail::wide_target<T> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_value_operation<N, detail::wide_generic_detail::wide_floor,T> && std::same_as<detail::wide_generic_detail::wide_result <detail::wide_generic_detail::wide_floor,T>,T>
constexpr wide< T, N >	floor (wide< T, N > const &input) noexcept(noexcept(detail::wide_generic_detail::wide_map< detail::wide_generic_detail::wide_floor >(input)))
template<class T, std::size_t N> requires (::native::detail::wide_target<T> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_value_operation<N, detail::wide_generic_detail::wide_ceil,T> && std::same_as<detail::wide_generic_detail::wide_result <detail::wide_generic_detail::wide_ceil,T>,T>
constexpr wide< T, N >	ceil (wide< T, N > const &input) noexcept(noexcept(detail::wide_generic_detail::wide_map< detail::wide_generic_detail::wide_ceil >(input)))
template<class T, std::size_t N> requires (::native::detail::wide_target<T> == NATIVE_WIDE_INDEX) && detail::wide_generic_detail::wide_value_operation<N, detail::wide_generic_detail::wide_trunc,T> && std::same_as<detail::wide_generic_detail::wide_result <detail::wide_generic_detail::wide_trunc,T>,T>
constexpr wide< T, N >	trunc (wide< T, N > const &input) noexcept(noexcept(detail::wide_generic_detail::wide_map< detail::wide_generic_detail::wide_trunc >(input)))
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX)
constexpr wide< R, N >	broadcast (R value) noexcept(noexcept(wide< R, N >::broadcast(value)))
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_abs(x); }
constexpr wide< R, N >	abs (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_abs(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_abs(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_abs(std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_sqrt(x); }
constexpr wide< R, N >	sqrt (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_sqrt(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_sqrt(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_sqrt(std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_sin(x); }
constexpr wide< R, N >	sin (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_sin(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_sin(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_sin(std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_cos(x); }
constexpr wide< R, N >	cos (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_cos(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_cos(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_cos(std::declval< R const & >())));}())
template<bool Flush = false, unsigned Degree = 6, class R, std::size_t N> requires (Degree >= 1 && Degree <= 7) && (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_exp<Flush,Degree>(x); }
constexpr wide< R, N >	exp (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_exp< Flush, Degree >(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_exp< Flush, Degree >(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_exp< Flush, Degree >(std::declval< R const & >())));}())
template<bool Flush = false, class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_exp2 <Flush>(x); }
constexpr wide< R, N >	exp2 (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_exp2< Flush >(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_exp2< Flush >(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_exp2< Flush >(std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_expm1(x); }
constexpr wide< R, N >	expm1 (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_expm1(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_expm1(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_expm1(std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_damping_gain(x); }
constexpr wide< R, N >	damping_gain (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_damping_gain(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_damping_gain(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_damping_gain(std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_log(x); }
constexpr wide< R, N >	log (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_log(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_log(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_log(std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_log2(x); }
constexpr wide< R, N >	log2 (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_log2(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_log2(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_log2(std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_log1p(x); }
constexpr wide< R, N >	log1p (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_log1p(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_log1p(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_log1p(std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_tanh(x); }
constexpr wide< R, N >	tanh (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_tanh(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_tanh(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_tanh(std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_atan2(x,x); }
constexpr wide< R, N >	atan2 (wide< R, N > const &y, wide< R, N > const &x) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_atan2(a, a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_atan2(std::declval< std::array< R, N > const & >(), std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_atan2(std::declval< R const & >(), std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_fma(x, x,x); }
constexpr wide< R, N >	fma (wide< R, N > const &a, wide< R, N > const &b, wide< R, N > const &c) noexcept([] { if constexpr(requires(std::array< R, N > const &x) { detail::wide_generic_detail::adl_fma(x, x, x);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_fma(std::declval< std::array< R, N > const & >(), std::declval< std::array< R, N > const & >(), std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_fma(std::declval< R const & >(), std::declval< R const & >(), std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_sincos(x); }
constexpr auto	sincos (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &x) { detail::wide_generic_detail::adl_sincos(x);}) return noexcept(detail::wide_generic_detail::adl_sincos(std::declval< std::array< R, N > const & >())) &&std::is_nothrow_move_constructible_v< std::array< R, N > >;else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|(noexcept(detail::wide_generic_detail::adl_sincos(std::declval< R const & >())) &&noexcept(std::declval< R & >()=std::declval< decltype(detail::wide_generic_detail::adl_sincos(std::declval< R const & >())) & >().first) &&noexcept(std::declval< R & >()=std::declval< decltype(detail::wide_generic_detail::adl_sincos(std::declval< R const & >())) & >().second)));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX)
constexpr wide< R, N >	select (wide< decltype(R{}==R{}), N > const &masks, wide< R, N > const &a, wide< R, N > const &b) noexcept([] { if constexpr(N==0) return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > >;else if constexpr(std::is_same_v< decltype(R{}==R{}), bool >) return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&noexcept(std::declval< R & >()=std::declval< R const & >());else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_select(std::declval< decltype(R{}==R{}) const & >(), std::declval< R const & >(), std::declval< R const & >()));}())
template<isa< arm > Arch> requires (Arch.has(arm_feature::crc))
constexpr std::uint32_t	crc32 (std::uint32_t accumulator, std::uint8_t value) noexcept
	Update the CRC32 accumulator with exactly 8 input bits.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::crc32))
constexpr std::uint32_t	crc32c (std::uint32_t accumulator, std::uint8_t value) noexcept
	Update a 32-bit CRC32C accumulator with exactly eight bits.
template<arch A>
constexpr auto	feature_closure (A input) noexcept
template<architecture Family = target_arch>
constexpr isa< Family >	target_features (std::string_view text) noexcept
template<class C> requires detail::normalized_features<C,x86> && requires(C const & c) { c.xcr0; c.xcr0_observed; }
constexpr isa_admission< x86 >	classify_isa (C const &cpu, isa< x86 > requested, isa< x86 > minimum={}) noexcept
template<auto... Entries, detail::capability_observation C, class F> requires ((decltype(detail::abi_match<Entries,0>::architecture)::family==detail::observation_family<C>) && ...)
constexpr bool	with_isa (isa_list< Entries... >, C const &cpu, F &&callback, isa< detail::observation_family< C > > minimum={})
	Admit the first available source variant and invoke callback.operator()().
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator& (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator> (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator>= (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator+ (simd< T, N, A >, simd< U, M, B >)=delete
	Reject mixed architectures and mismatched short-vector widths before native conversions can participate.
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_sin(x); }
constexpr wide< R, N >	sin (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_sin(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_sin(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_sin(std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_cos(x); }
constexpr wide< R, N >	cos (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_cos(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_cos(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_cos(std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_sincos(x); }
constexpr auto	sincos (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &x) { detail::wide_generic_detail::adl_sincos(x);}) return noexcept(detail::wide_generic_detail::adl_sincos(std::declval< std::array< R, N > const & >())) &&std::is_nothrow_move_constructible_v< std::array< R, N > >;else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|(noexcept(detail::wide_generic_detail::adl_sincos(std::declval< R const & >())) &&noexcept(std::declval< R & >()=std::declval< decltype(detail::wide_generic_detail::adl_sincos(std::declval< R const & >())) & >().first) &&noexcept(std::declval< R & >()=std::declval< decltype(detail::wide_generic_detail::adl_sincos(std::declval< R const & >())) & >().second)));}())
template<bool Flush = false, unsigned Degree = 6, std::size_t L, ::native::isa<> Arch> requires (Degree >= 1 && Degree <= 7) && (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<L>
constexpr simd< float, L, Arch >	exp (simd< float, L, Arch > input) noexcept
	Evaluate the binary32 range-reduced exponential approximation. Degree selects a polynomial from one through seven, defaulting to six. Every degree shares range reduction and exponent scaling; none promises correctly rounded exp for every input. Flush selects the early underflow cutoff at compile time; it does not change CPU controls or turn a raw vector into a policy-bearing FTZ type.
template<bool Flush = false, std::size_t L, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<L>
constexpr simd< float, L, Arch >	exp2 (simd< float, L, Arch > input) noexcept
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_expm1(x); }
constexpr wide< R, N >	expm1 (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_expm1(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_expm1(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_expm1(std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_damping_gain(x); }
constexpr wide< R, N >	damping_gain (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_damping_gain(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_damping_gain(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_damping_gain(std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_log(x); }
constexpr wide< R, N >	log (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_log(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_log(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_log(std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_log2(x); }
constexpr wide< R, N >	log2 (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_log2(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_log2(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_log2(std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_log1p(x); }
constexpr wide< R, N >	log1p (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_log1p(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_log1p(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_log1p(std::declval< R const & >())));}())
template<class R, std::size_t N> requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_tanh(x); }
constexpr wide< R, N >	tanh (wide< R, N > const &input) noexcept([] { if constexpr(requires(std::array< R, N > const &a) { detail::wide_generic_detail::adl_tanh(a);}) return noexcept(wide< R, N >{detail::wide_generic_detail::adl_tanh(std::declval< std::array< R, N > const & >())});else return noexcept(wide< R, N >()) &&std::is_nothrow_move_constructible_v< wide< R, N > > &&(N==0\|\|noexcept(std::declval< R & >()=detail::wide_generic_detail::adl_tanh(std::declval< R const & >())));}())
template<std::size_t L, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<L>
constexpr simd< float, L, Arch >	atan2 (simd< float, L, Arch > y, simd< float, L, Arch > x) noexcept
constexpr bool	isnan (::native::fp16 x) noexcept
	Classify the stored bits as NaN without performing a floating-point conversion.
constexpr std::span< std::uint8_t const >	wasm_feature_probe (wasm_feature feature) noexcept
constexpr wasm_capabilities	decode_wasm_capabilities (wasm_capabilities::raw_observations raw) noexcept
template<class V> requires requires(V & validate,std::span<std::uint8_t const> bytes) { { validate(bytes) } noexcept -> std::same_as<std::optional <bool>>; }
constexpr wasm_capabilities	observe_wasm_capabilities (V &&validate) noexcept
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::adx))
constexpr std::uint8_t	addcarryx (std::uint8_t carry, std::uint32_t a, std::uint32_t b, std::uint32_t *result) noexcept
	Add 32-bit operands with carry, writing the modular result.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint32_t	andn (std::uint32_t first, std::uint32_t second) noexcept
	Re-export ANDN; see the BMI1 group for both operand widths.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint32_t	bextr (std::uint32_t value, std::uint32_t control) noexcept
	Re-export BEXTR; see the BMI1 group for packed and separate controls.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint32_t	blsi (std::uint32_t value) noexcept
	Re-export BLSI; see the BMI1 group for both operand widths.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint32_t	blsmsk (std::uint32_t value) noexcept
	Re-export BLSMSK; see the BMI1 group for both operand widths.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint32_t	blsr (std::uint32_t value) noexcept
	Re-export BLSR; see the BMI1 group for both operand widths.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi1))
constexpr std::uint16_t	tzcnt (std::uint16_t value) noexcept
	Re-export TZCNT; see the BMI1 group for all three operand widths.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	bzhi (std::uint32_t value, unsigned index) noexcept
	Re-export BZHI; see the BMI2 group for both operand widths.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	mulx (std::uint32_t a, std::uint32_t b, std::uint32_t *high) noexcept
	Re-export MULX; see the BMI2 group for both product widths.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	pdep (std::uint32_t value, std::uint32_t maskmask) noexcept
	Re-export PDEP; see the BMI2 group for both operand widths.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	pext (std::uint32_t value, std::uint32_t maskmask) noexcept
	Re-export PEXT; see the BMI2 group for both operand widths.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	shlx (std::uint32_t value, unsigned count) noexcept
	Re-export SHLX; see the BMI2 group for both operand widths.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	shrx (std::uint32_t value, unsigned count) noexcept
	Re-export SHRX; see the BMI2 group for both operand widths.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::int32_t	sarx (std::int32_t value, unsigned count) noexcept
	Re-export SARX; see the BMI2 group for both signed operand widths.
template<unsigned Imm8, isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2) && Imm8 <= 255)
constexpr std::uint32_t	rorx (std::uint32_t value) noexcept
	Re-export RORX; see the BMI2 group for immediate rotation counts.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::crc32))
constexpr std::uint32_t	crc32c (std::uint32_t accumulator, std::uint8_t value) noexcept
	Update a 32-bit CRC32C accumulator with exactly eight bits.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::lzcnt))
constexpr std::uint16_t	lzcnt (std::uint16_t value) noexcept
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::popcnt))
constexpr std::uint16_t	popcnt (std::uint16_t value) noexcept
template<class V, class U, std::size_t A = 1, simd_access Access = simd_access::ordinary> requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) && requires(U const * p) { V::template load_memory<A>(p); }
constexpr V	load_simd (U const *p, simd_memory< A, Access >={}) noexcept(noexcept(V::template load_memory< A >(p)))
template<class V, class U, std::size_t A = 1, simd_access Access = simd_access::ordinary> requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) && std::default_initializable<U> && std::constructible_from<U,typename V::value_type &> && std::is_copy_assignable_v<U> && requires(U const * p) { ::native::load_simd<V>(p); }
constexpr V	load_simd_partial (U const *p, std::size_t count, typename V::value_type fill={}, simd_memory< A, Access >={}) noexcept(std::is_nothrow_default_constructible_v< U > &&std::is_nothrow_constructible_v< U, typename V::value_type & > &&std::is_nothrow_copy_assignable_v< U > &&noexcept(::native::load_simd< V >(p)))
template<class U, class V, std::size_t A = 1, simd_access Access = simd_access::ordinary> requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) && requires(V value,U * p) { value.template store_memory<A>(p); }
constexpr void	store_simd (U *p, V value, simd_memory< A, Access >={}) noexcept(noexcept(value.template store_memory< A >(p)))
template<class U, class V, std::size_t A = 1, simd_access Access = simd_access::ordinary> requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) && std::default_initializable<U> && std::is_copy_assignable_v<U> && requires(U * p,V value) { ::native::store_simd(p,value); }
constexpr void	store_simd_partial (U *p, V value, std::size_t count, simd_memory< A, Access >={}) noexcept(std::is_nothrow_default_constructible_v< U > &&std::is_nothrow_copy_assignable_v< U > &&noexcept(::native::store_simd(p, value)))
template<class T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (std::same_as<T,float> \|\| std::same_as<T,std::int32_t> \|\| std::same_as<T,std::uint32_t>) && ::native::detail::avx512_backend::float_shape<N>
constexpr compaction_result< simd< T, N, Arch > >	compress (typename simd< T, N, Arch >::mask maskmask, simd< T, N, Arch > value, T fill=T{}) noexcept
template<class T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (std::same_as<T,float> \|\| std::same_as<T,std::int32_t> \|\| std::same_as<T,std::uint32_t>) && ::native::detail::avx512_backend::float_shape<N>
constexpr simd< T, N, Arch >	expand (typename simd< T, N, Arch >::mask maskmask, simd< T, N, Arch > packed, simd< T, N, Arch > prior) noexcept
template<class T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (std::same_as<T,float> \|\| std::same_as<T,std::int32_t> \|\| std::same_as<T,std::uint32_t>) && ::native::detail::avx512_backend::float_shape<N>
constexpr std::size_t	compress_store (T *destination, std::size_t capacity, typename simd< T, N, Arch >::mask maskmask, simd< T, N, Arch > value) noexcept
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator+ (simd< T, N, A >, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator- (simd< T, N, A >, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator* (simd< T, N, A >, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator/ (simd< T, N, A >, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator% (simd< T, N, A >, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator& (simd< T, N, A >, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator\| (simd< T, N, A >, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator^ (simd< T, N, A >, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator>> (simd< T, N, A >, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, std::size_t N> requires (::native::detail::wide_target<T> == NATIVE_WIDE_INDEX) && requires(T const & a) { !a; }
constexpr auto	operator! (wide< T, N > const &a)
	Make the corresponding native overload set visible through this module.
template<class T, std::size_t N> requires (::native::detail::wide_target<T> == NATIVE_WIDE_INDEX) && requires(T const & a) { ~a; }
constexpr auto	operator~ (wide< T, N > const &a)
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator== (simd< T, N, A >, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator!= (simd< T, N, A >, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator> (simd< T, N, A >, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator>= (simd< T, N, A >, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator+= (simd< T, N, A > &, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator-= (simd< T, N, A > &, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator*= (simd< T, N, A > &, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator/= (simd< T, N, A > &, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator%= (simd< T, N, A > &, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator&= (simd< T, N, A > &, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator\|= (simd< T, N, A > &, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator^= (simd< T, N, A > &, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B> requires (A!=B \|\| (N!=M && (N==2 \|\| N==3 \|\| M==2 \|\| M==3)))
void	operator>>= (simd< T, N, A > &, simd< U, M, B >)=delete
	Make the corresponding native overload set visible through this module.
template<class To, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && std::same_as<To,std::int32_t>
constexpr simd< To, N, Arch >	convert (simd< float, N, Arch > x) noexcept
template<simd_integer_element To, simd_integer_element From, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (sizeof(From) * N % sizeof(To) == 0 && requires { typename simd<From,N,Arch>::native_type; typename simd<To,sizeof(From)N/sizeof(To),Arch>::native_type; } && sizeof(typename simd<From,N,Arch>::native_type) == sizeof(typename simd<To,sizeof(From)N/sizeof(To),Arch>::native_type) && (sizeof(typename simd<From,N,Arch> ::native_type) <= 16 \|\| sizeof(typename simd<From,N,Arch>::native_type) == 32 \|\| sizeof(typename simd<From,N,Arch> ::native_type) == 64 ))
constexpr auto	reinterpret_bits (simd< From, N, Arch > value) noexcept -> simd< To, sizeof(From) *N/sizeof(To), Arch >
template<simd_integer_element T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (std::is_unsigned_v<T> && detail::integer_arithmetic<T,N,Arch>)
constexpr simd< T, N, Arch >	popcount (simd< T, N, Arch > value) noexcept
template<simd_integer_element T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (std::is_unsigned_v<T> && sizeof(T) <= 4 && N > 1 && N % 2 == 0 && detail::integer_arithmetic<T,N,Arch>)
constexpr auto	pairwise_add_widened (simd< T, N, Arch > value) noexcept
template<simd_integer_element T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (std::is_unsigned_v<T> && sizeof(T)<=4 && detail::integer_arithmetic<T,N,Arch>)
constexpr std::uint64_t	reduce_add_widened (simd< T, N, Arch > value) noexcept
template<simd_mask_element M, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch )
constexpr auto	mask_bits (simd< M, N, Arch > m) noexcept
template<class U, class T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && simd_mask_element<U> && simd_mask_element<T> && requires { typename simd<U,N,Arch> ::native_type; typename simd<T,N,Arch>::native_type; }
constexpr simd< U, N, Arch >	mask_cast (simd< T, N, Arch > value) noexcept
template<class T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && simd_mask_element<T> && requires { typename simd<bool,N,Arch>::native_type; typename simd <T,N,Arch>::native_type; }
constexpr simd< bool, N, Arch >	to_bool (simd< T, N, Arch > value) noexcept
	Convert lane truth into Boolean data lanes represented as zero or one, preserving the lane count.
template<class T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && simd_mask_element<T> && ::native::detail::avx512_backend::predicate_shape<N> && requires { typename simd<T,N,Arch>::native_type; }
constexpr predicate< N, Arch >	to_predicate (simd< T, N, Arch > value) noexcept
template<class T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && simd_mask_element<T> && ::native::detail::avx512_backend::predicate_shape<N> && requires { typename simd<T,N,Arch>::native_type; }
constexpr simd< T, N, Arch >	to_vector_mask (predicate< N, Arch > value) noexcept
template<simd_integer_element T, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::integer_shape<T, N>
constexpr simd< T, N, Arch >	bit_select (simd< T, N, Arch > bits, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Make the corresponding native overload set visible through this module.
template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> && ::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)
constexpr simd< T, N, Arch >	select (M m, simd< T, N, Arch > a, simd< T, N, Arch > b)
template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> && ::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)
constexpr simd< T, N, Arch >	masked_add (M m, simd< T, N, Arch > prior, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Make the corresponding native overload set visible through this module.
template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> && ::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)
constexpr simd< T, N, Arch >	masked_add_zero (M m, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> && ::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)
constexpr simd< T, N, Arch >	masked_sub (M m, simd< T, N, Arch > prior, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Make the corresponding native overload set visible through this module.
template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> && ::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)
constexpr simd< T, N, Arch >	masked_sub_zero (M m, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> && ::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)
constexpr simd< T, N, Arch >	masked_mul (M m, simd< T, N, Arch > prior, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
	Make the corresponding native overload set visible through this module.
template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> && ::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)
constexpr simd< T, N, Arch >	masked_mul_zero (M m, simd< T, N, Arch > a, simd< T, N, Arch > b) noexcept
template<std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::native_scaleb_shape<N> &&(std::same_as<M,typename simd <float,N,Arch>::mask_type> \|\| std::same_as<M,typename simd<float,N,Arch>::vector_mask_type>)
constexpr simd< float, N, Arch >	masked_scaleb (M maskmask, simd< float, N, Arch > prior, simd< float, N, Arch > value, simd< float, N, Arch > exponent) noexcept
template<std::size_t N, class M, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::native_scaleb_shape<N> &&(std::same_as<M,typename simd <float,N,Arch>::mask_type> \|\| std::same_as<M,typename simd<float,N,Arch>::vector_mask_type>)
constexpr simd< float, N, Arch >	masked_scaleb_zero (M maskmask, simd< float, N, Arch > value, simd< float, N, Arch > exponent) noexcept
template<std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::native_scaleb_shape<N>
constexpr simd< float, N, Arch >	scaleb (simd< float, N, Arch > value, simd< float, N, Arch > exponent) noexcept
template<::native::isa<> Arch> requires (::native::avx512 <= Arch )
constexpr simd< fp16, 32, Arch >	fma (simd< fp16, 32, Arch > a, simd< fp16, 32, Arch > b, simd< fp16, 32, Arch > c) noexcept
template<std::size_t I, detail::wasm_number T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16) && (I < N)
constexpr simd< T, N, A >	broadcast (simd< T, N, A > v, imm_t< I >) noexcept
	Broadcast one compile-time-selected lane.
template<std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N>
constexpr auto	abs (simd< float, N, Arch > a) noexcept
template<std::floating_point T, std::size_t N, isa<> A> requires (A.has(wasm_feature::simd128)) && (sizeof(T) * N == 16)
constexpr simd< T, N, A >	sqrt (simd< T, N, A > v) noexcept
	Compute correctly rounded square roots; negative finite lanes produce NaN.
template<std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N>
constexpr simd< float, N, Arch >	floor (simd< float, N, Arch > x) noexcept
template<std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N>
constexpr simd< float, N, Arch >	ceil (simd< float, N, Arch > x) noexcept
template<std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N>
constexpr simd< float, N, Arch >	trunc (simd< float, N, Arch > x) noexcept
template<simd_integer_element To, simd_integer_element From, std::size_t N, ::native::isa<> Arch> requires (::native::avx512 <= Arch ) && (std::is_unsigned_v<To> && std::is_unsigned_v<From> && sizeof(From) == 2 * sizeof(To) && // The selected backend must implement this width. Complete storage alone // does not establish the arithmetic instructions used by this operation. (N * sizeof(From) == 16 \|\| N * sizeof(From) == 32 \|\| (N * sizeof(From) == 64 && (sizeof(From) >= 4 \|\| 1 != 0)) ) && requires { sizeof(simd<From, N, Arch>); sizeof(simd<To, 2 * N, Arch>); })
constexpr simd< To, 2 *N, Arch >	narrow_concat (simd< From, N, Arch > a, simd< From, N, Arch > b) noexcept
template<fp32_bits_register V, std::size_t N>
constexpr std::array< V, N >	flush_to_zero (std::array< V, N > const &x) noexcept
	Replace binary32 subnormal lanes with signed zero. Both zero signs, normal values, infinities and every NaN payload/sign are preserved exactly. This changes the values, not the floating-point control state, and does not raise floating-point exceptions. Empty arrays are valid.

Variables
constexpr std::size_t	max_fp_comparison_predicate
template<typename T>
std::string_view const	type
enum cpu_vendor	cpu_vendor
	Cached vendor identification; vendor alone does not establish features.
constexpr architecture	x86 =architecture::x86
	Select x86 feature metadata independently of the compilation target.
constexpr architecture	arm =architecture::arm
	Select ARM feature metadata independently of the compilation target.
constexpr architecture	wasm =architecture::wasm
	Select WebAssembly feature metadata independently of the compilation target.
constexpr architecture	target_arch
	The compiler target's family; no optional instruction support is implied.
template<std::size_t K>
constexpr imm_t< K >	imm {}
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	exp_width
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	exp2_width = detail::math_branching_width<T, K, A>
	Recommended exp2 register count; its shorter reduction favors small batches.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	expm1_width = detail::math_polynomial_width<T, K, A>
	Conservative independent register count for cancellation-safe expm1.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	damping_gain_width = expm1_width<T, K, A>
	Suggested damping_gain register count, matching its expm1 graph.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	log_width = detail::math_polynomial_width<T, K, A>
	Conservative independent register count for the logarithm kernel.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	log2_width = log_width<T, K, A>
	Suggested log2 register count, matching the logarithm recommendation.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	log1p_width = detail::math_polynomial_width<T, K, A>
	Conservative independent register count for cancellation-safe log1p.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	tanh_width = detail::math_branching_width<T, K, A>
	Conservative independent register count for tanh's table and polynomial.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	atan2_width = detail::math_branching_width<T, K, A>
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	sincos_width
	Recommended independent register count for paired sine and cosine.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	sin_width = sincos_width<T, K, A>
	Suggested sine register count, matching the paired trigonometric kernel.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	cos_width = sincos_width<T, K, A>
	Suggested cosine register count, matching the paired trigonometric kernel.
constexpr std::size_t	wasm_feature_count =std::size_t(wasm_feature::relaxed_simd)+1
	Number of named Wasm feature values.
constexpr std::size_t	x86_feature_count =std::size_t(x86_feature::avxneconvert)+1
	Number of named x86 feature values.
constexpr std::size_t	arm_feature_count =std::size_t(arm_feature::sm4)+1
	Number of named ARM feature values.
template<auto A, auto... Choices>
constexpr int	target
	First matching requirement, with every later choice checked for shadowing.
constexpr architecture	x86
	Select x86 feature metadata independently of the compilation target.
constexpr architecture	arm
	Select ARM feature metadata independently of the compilation target.
constexpr architecture	wasm
	Select WebAssembly feature metadata independently of the compilation target.
constexpr architecture	target_arch
	The compiler target's family; no optional instruction support is implied.
constexpr std::size_t	x86_feature_count
	Number of named x86 feature values.
constexpr std::size_t	arm_feature_count
	Number of named ARM feature values.
constexpr std::size_t	wasm_feature_count
	Number of named Wasm feature values.
template<auto A, auto... Choices>
constexpr int	target
	First matching requirement, with every later choice checked for shadowing.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	exp_width
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	exp2_width
	Recommended exp2 register count; its shorter reduction favors small batches.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	expm1_width
	Conservative independent register count for cancellation-safe expm1.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	damping_gain_width
	Suggested damping_gain register count, matching its expm1 graph.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	log_width
	Conservative independent register count for the logarithm kernel.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	log2_width
	Suggested log2 register count, matching the logarithm recommendation.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	log1p_width
	Conservative independent register count for cancellation-safe log1p.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	tanh_width
	Conservative independent register count for tanh's table and polynomial.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	atan2_width
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	sincos_width
	Recommended independent register count for paired sine and cosine.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	sin_width
	Suggested sine register count, matching the paired trigonometric kernel.
template<class T, std::size_t K, isa A = NATIVE_BASELINE>
constexpr std::size_t	cos_width
	Suggested cosine register count, matching the paired trigonometric kernel.
template<std::size_t K>
constexpr imm_t< K >	imm
template<std::size_t K>
constexpr imm_t< K >	imm
template<std::size_t K>
constexpr imm_t< K >	imm

Detailed Description

Architecture-tagged vectors, register packs and supporting value types. Native arithmetic follows its architecture tag and instruction-set preconditions. Common utilities do not select or admit a runtime CPU profile.

Enumeration Type Documentation

◆ cpu_vendor

enum class enum cpu_vendor native::cpu_vendor

exportstrong

Initial value:

                     = [] static noexcept {
  return detail::identify_vendor(detail::vendor_identifier(cpuid(0,0)));
}()

Recognized CPUID vendor strings; vendor identity alone does not imply features.

Values classify leaf zero only and are independent of OS vector-state support.

Enumerator
intel	0	CPUID reports GenuineIntel.
amd	1	CPUID reports AuthenticAMD.
unknown	2	Any other vendor string.

Definition at line 40 of file native.x86.features.ccm.

◆ simd_access [1/2]

enum class native::simd_access

strong

Requested access policy. Streaming currently uses ordinary memory access.

Definition at line 280 of file common.h.

◆ simd_access [2/2]

enum class native::simd_access

strong

Requested access policy. Streaming currently uses ordinary memory access.

Definition at line 280 of file common.h.

Function Documentation

◆ abs()

template<std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N>

auto native::abs ( simd< float, N, Arch > a )

inlineconstexprnoexcept

Clear each binary32 sign bit, preserving the remaining payload bits.

Definition at line 4475 of file simd_family.h.

◆ atan2()

template<std::size_t L, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<L>

simd< float, L, Arch > native::atan2	(	simd< float, L, Arch >	y,
		simd< float, L, Arch >	x )

inlineconstexprnoexcept

Evaluate atan2(y,x), retaining the common SIMD architecture and lane count.

Definition at line 91 of file exp_body.h.

◆ ceil()

template<std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N>

simd< float, N, Arch > native::ceil ( simd< float, N, Arch > x )

inlineconstexprnoexcept

Round each lane toward positive infinity, independently of ambient rounding. Signed zeros and infinities are preserved; NaNs remain NaNs. Raw denormal handling still follows the CPU environment. No NaN payload or FP-status promise is added.

template<native::isa<> Arch>
void rounding() {
  using V = native::simd<float, 4, Arch>;
  V x{-1.75f, -0.25f, 0.25f, 1.75f};
  check(all(native::floor(x) == V{-2.f, -1.f, 0.f, 1.f}));
  check(all(native::ceil(x) == V{-1.f, -0.f, 1.f, 2.f}));
  check(all(native::trunc(x) == V{-1.f, -0.f, 0.f, 1.f}));
}

Definition at line 5158 of file simd_family.h.

◆ classify_isa() [1/6]

template<detail::arm_observation C>
requires (!detail::has_feature_observation<C>)

isa_admission< arm > native::classify_isa	(	C const &	cpu,
		isa< arm >	requested,
		isa< arm >	minimum = {} )

constexprnoexcept

Decode a structural raw ARM snapshot before applying the same admission rules. Failed OS queries cannot authorize stale positive values.

Definition at line 742 of file isa.h.

◆ classify_isa() [2/6]

template<class C>
requires detail::normalized_features<C,arm>

isa_admission< arm > native::classify_isa	(	C const &	cpu,
		isa< arm >	requested,
		isa< arm >	minimum = {} )

constexprnoexcept

Classify normalized ARM features. A feature must be both present and observed. Raw query diagnostics do not override the normalized observation.

Definition at line 717 of file isa.h.

◆ classify_isa() [3/6]

template<detail::x86_observation C>
requires (!detail::has_feature_observation<C>) && requires(C const & c) { c.xcr0; c.xcr0_observed; }

isa_admission< x86 > native::classify_isa	(	C const &	cpu,
		isa< x86 >	requested,
		isa< x86 >	minimum = {} )

constexprnoexcept

Decode a structural raw x86 snapshot before applying the same admission rules. Unsupported leaves and unread XCR0 cannot authorize stale positive values.

Definition at line 731 of file isa.h.

◆ classify_isa() [4/6]

template<class C>
requires detail::normalized_features<C,x86> && requires(C const & c) { c.xcr0; c.xcr0_observed; }

isa_admission< x86 > native::classify_isa	(	C const &	cpu,
		isa< x86 >	requested,
		isa< x86 >	minimum = {} )

constexprnoexcept

Classify normalized x86 features and independently observed OS vector state. Both present and observed must contain each required feature. Raw diagnostics are not read; changing them does not change the normalized observation.

Definition at line 709 of file isa.h.

Here is the caller graph for this function:

◆ classify_isa() [5/6]

template<class C>
requires detail::normalized_features<C,x86> && requires(C const & c) { c.xcr0; c.xcr0_observed; }

isa_admission< x86 > native::classify_isa	(	C const &	cpu,
		isa< x86 >	requested,
		isa< x86 >	minimum = {} )

constexprnoexcept

Classify normalized x86 features and independently observed OS vector state. Both present and observed must contain each required feature. Raw diagnostics are not read; changing them does not change the normalized observation.

Definition at line 709 of file isa.h.

◆ classify_isa() [6/6]

template<class C>
requires detail::normalized_features<C,wasm>

isa_admission< wasm > native::classify_isa	(	C const &	runtime,
		isa< wasm >	requested,
		isa< wasm >	minimum = {} )

constexprnoexcept

Classify normalized Wasm observations. Relaxed SIMD also requires SIMD128. Unknown observations reject; raw diagnostics and compiler flags are not read.

Definition at line 724 of file isa.h.

◆ compress()

template<class T, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && (std::same_as<T,float> || std::same_as<T,std::int32_t> || std::same_as<T,std::uint32_t>) &&
::native::detail::avx512_backend::float_shape<N>

compaction_result< simd< T, N, Arch > > native::compress	(	typename simd< T, N, Arch >::mask	mask,
		simd< T, N, Arch >	value,
		T	fill = T{} )

inlineconstexprnoexcept

Pack selected logical lanes in increasing order; fill all remaining lanes. This rearranges bits, including NaN payloads and signed zeros. Short padding never contributes to count or output and is zero in the result.

template<native::isa<> Arch>
void compaction() {
  using V = native::simd<std::uint32_t, 4, Arch>;
  auto active = V::mask::from_bitset(0b1010);
  V input{10u, 20u, 30u, 40u};
  auto packed = native::compress(active, input, 99u);
  check(packed.count == 2 && all(packed.value == V{20u, 40u, 99u, 99u}));
  auto restored = native::expand(active, packed.value, V(77u));
  check(all(restored == V{77u, 20u, 77u, 40u}));
  std::array<std::uint32_t, 2> output{0u, 123u};
  auto written = native::compress_store(output.data(), 1, active, input);
  check(written == 1 && output[0] == 20u && output[1] == 123u);
}

Definition at line 5313 of file simd_family.h.

◆ compress_store()

template<class T, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && (std::same_as<T,float> || std::same_as<T,std::int32_t> || std::same_as<T,std::uint32_t>) &&
::native::detail::avx512_backend::float_shape<N>

std::size_t native::compress_store	(	T *	destination,
		std::size_t	capacity,
		typename simd< T, N, Arch >::mask	mask,
		simd< T, N, Arch >	value )

inlineconstexprnoexcept

Write the first min(capacity,popcount(mask)) selected lanes, in input order. Return the number WRITTEN, not the total selected count. No element beyond that prefix is accessed. Null is valid when capacity or the mask is zero.

Definition at line 5357 of file simd_family.h.

◆ convert() [1/2]

template<class To, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N> && std::same_as<To,std::int32_t>

simd< To, N, Arch > native::convert ( simd< float, N, Arch > x )

inlineconstexprnoexcept

Convert floats to signed 32-bit integers by truncation toward zero.

Precondition: Every truncated result is representable; NaNs and infinities are outside the contract.

Definition at line 4562 of file simd_family.h.

◆ convert() [2/2]

template<std::floating_point To, detail::wasm_number From, std::size_t N, isa<> A>
requires (A.has(wasm_feature::simd128)) && (sizeof(From) * N == 16 && (sizeof(From) == 4 || std::is_floating_point_v<From>) &&
!std::same_as<To, From>)

simd< To, 16/sizeof(To), A > native::convert ( simd< From, N, A > a )

inlineconstexprnoexcept

Native integer-to-float or float-width conversion. Double results consume the low two source lanes; float demotion zeroes its upper two lanes.

Definition at line 7126 of file simd_family.h.

◆ cos()

template<class R, std::size_t N>
requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_cos(x); }

wide< R, N > native::cos ( wide< R, N > const & input )

inlineconstexprnoexcept

Apply the element library's cosine operation in radians. Uses one array call when available, otherwise an elementwise fallback.

Definition at line 1024 of file wide.h.

◆ cvtss_sh()

template<unsigned Imm8, isa< x86 > Arch = NATIVE_BASELINE>
requires (Arch.has(x86_feature::f16c) && Imm8 <= 255)

std::uint16_t native::cvtss_sh ( float a )

inlineconstexprexportnoexcept

Convert one binary32 value using the module baseline or an explicit ISA. Both cvtss_sh<Imm8, Arch> and cvtss_sh<Arch, Imm8> select the same operation.

Definition at line 171 of file native.x86.f16c.ccm.

◆ damping_gain()

template<class R, std::size_t N>
requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x)
{ detail::wide_generic_detail::adl_damping_gain(x); }

wide< R, N > native::damping_gain ( wide< R, N > const & input )

inlineconstexprnoexcept

Apply the element library's -expm1(-x) operation. Uses one array call when available, otherwise an elementwise fallback.

Definition at line 1109 of file wide.h.

◆ decode_wasm_capabilities()

wasm_capabilities native::decode_wasm_capabilities ( wasm_capabilities::raw_observations raw )

constexprnoexcept

Normalize independent observations without inferring missing answers. classify_isa separately requires SIMD128 when relaxed SIMD is requested.

Definition at line 65 of file features.h.

◆ dot2() [1/2]

template<::native::isa<> Arch>
requires (::native::avx512 <= Arch )

simd< float, 4, Arch > native::dot2	(	simd< bf16, 8, Arch >	a,
		simd< bf16, 8, Arch >	b,
		simd< float, 4, Arch >	accumulator )

inlineconstexprexportnoexcept

Native BFDOT: output i combines adjacent products a[2*i]*b[2*i] and a[2*i+1]*b[2*i+1], then adds accumulator[i]. This follows Arm's native instruction, not the x86 dot2 rounding/order contract or scalar conversions. With EBF absent/clear, products, their sum and accumulation round separately to odd with overflow to infinity; denormal inputs/results flush to zero. AH affects only the default NaN sign in this mode. With FEAT_EBF16 and FPCR.EBF set, the pair is fused and rounded before separate accumulation; FPCR.RMode/FZ/AH/FIZ govern standard single-precision behavior. Both modes return default NaNs, ignore exception enables, and leave FPSR unchanged. No operation changes FPCR. Applications own FPCR and ISA admission; this API makes no reproducible cross-ISA or cross-FPCR result promise.

Definition at line 577 of file native.simd.ccm.

◆ dot2() [2/2]

template<std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) &&(N == 8 || N == 16 || N == 32)

simd< float, N/2, Arch > native::dot2	(	simd< bf16, N, Arch >	a,
		simd< bf16, N, Arch >	b,
		simd< float, N/2, Arch >	accumulator )

inlineconstexprexportnoexcept

Native VDPBF16PS: for each output i, accumulate a[2*i+1]*b[2*i+1] first, then a[2*i]*b[2*i]. Each FP32 FMA rounds to nearest, ties to even; input denormals are zero and output denormals are flushed to zero. MXCSR is neither consulted nor updated, including exception status. This is not a single-rounding three-term sum. NaN propagation follows the instruction, with low input lanes taking priority over high lanes.

Definition at line 180 of file native.simd.ccm.

Here is the caller graph for this function:

◆ exp()

template<bool Flush = false, unsigned Degree = 6, std::size_t L, ::native::isa<> Arch>
requires (Degree >= 1 && Degree <= 7) && (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<L>

simd< float, L, Arch > native::exp ( simd< float, L, Arch > input )

inlineconstexprnoexcept

Evaluate the binary32 range-reduced exponential approximation. Degree selects a polynomial from one through seven, defaulting to six. Every degree shares range reduction and exponent scaling; none promises correctly rounded exp for every input. Flush selects the early underflow cutoff at compile time; it does not change CPU controls or turn a raw vector into a policy-bearing FTZ type.

template<native::isa<> Arch>
void exponential() {
  using V = native::simd<float, 4, Arch>;
  std::array<V, 2> registers{V(0.f), V(1.f)};
  auto result = native::exp(registers);
  auto powers = native::exp2(registers);
  check(all(powers[0] == V(1.f)) && all(powers[1] == V(2.f)));
  auto exponents = native::log2(powers);
  check(all(exponents[0] == V(0.f)) && all(exponents[1] == V(1.f)));
  check(all(result[0] == V(1.f)));
  check(all(result[1] > V(2.718f)) && all(result[1] < V(2.719f)));
}

Definition at line 109 of file exp_body.h.

◆ exp2()

template<bool Flush = false, std::size_t L, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<L>

simd< float, L, Arch > native::exp2 ( simd< float, L, Arch > input )

inlineconstexprnoexcept

Base-two exponential with the same compile-time underflow policy as exp.

Definition at line 65 of file exp_body.h.

◆ expand()

template<class T, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && (std::same_as<T,float> || std::same_as<T,std::int32_t> || std::same_as<T,std::uint32_t>) &&
::native::detail::avx512_backend::float_shape<N>

simd< T, N, Arch > native::expand	(	typename simd< T, N, Arch >::mask	mask,
		simd< T, N, Arch >	packed,
		simd< T, N, Arch >	prior )

inlineconstexprnoexcept

Consume packed's first popcount(mask) lanes in order at selected positions. Unselected lanes retain prior bitwise. Short physical padding is zeroed.

Definition at line 5335 of file simd_family.h.

◆ expm1()

template<class R, std::size_t N>
requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x)
{ detail::wide_generic_detail::adl_expm1(x); }

wide< R, N > native::expm1 ( wide< R, N > const & input )

inlineconstexprnoexcept

Apply the element library's exp(x)-1 operation. Uses one array call when available, otherwise an elementwise fallback.

Definition at line 1088 of file wide.h.

◆ fast_to_bf16()

bf16 native::fast_to_bf16 ( float f )

inlineconstexprexportnoexcept

Compatibility fast conversion: runtime drops the low sixteen binary32 bits. Constant evaluation uses the ordinary rounded constructor instead. Use bf16(f) when both contexts must share rounding or NaN handling.

Definition at line 446 of file native.numerics.ccm.

Here is the caller graph for this function:

◆ feature_closure() [1/2]

template<arch A>

auto native::feature_closure ( A input )

constexprnoexcept

Add the same family's register and instruction prerequisites. ARM crypto siblings remain independent; target_features adds compiler bundles.

Definition at line 538 of file isa.h.

Here is the caller graph for this function:

◆ feature_closure() [2/2]

template<arch A>

auto native::feature_closure ( A input )

constexprnoexcept

Add the same family's register and instruction prerequisites. ARM crypto siblings remain independent; target_features adds compiler bundles.

Definition at line 538 of file isa.h.

◆ floor()

template<std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N>

simd< float, N, Arch > native::floor ( simd< float, N, Arch > x )

inlineconstexprnoexcept

Round each lane toward negative infinity, independently of ambient rounding. Signed zeros and infinities are preserved; NaNs remain NaNs. Raw denormal handling still follows the CPU environment. No NaN payload or FP-status promise is added.

template<native::isa<> Arch>
void rounding() {
  using V = native::simd<float, 4, Arch>;
  V x{-1.75f, -0.25f, 0.25f, 1.75f};
  check(all(native::floor(x) == V{-2.f, -1.f, 0.f, 1.f}));
  check(all(native::ceil(x) == V{-1.f, -0.f, 1.f, 2.f}));
  check(all(native::trunc(x) == V{-1.f, -0.f, 0.f, 1.f}));
}

Definition at line 5142 of file simd_family.h.

◆ flush_to_zero()

template<fp32_bits_register V, std::size_t N>

std::array< V, N > native::detail::avx512_backend::native::flush_to_zero ( std::array< V, N > const & x )

inlineconstexprnoexcept

Replace binary32 subnormal lanes with signed zero. Both zero signs, normal values, infinities and every NaN payload/sign are preserved exactly. This changes the values, not the floating-point control state, and does not raise floating-point exceptions. Empty arrays are valid.

template<native::isa<> Arch>
void bit_transport() {
  using V = native::simd<float, 4, Arch>;
  auto tiny = V::from_bits(0x80000001u);
  auto zero = native::flush_to_zero(tiny);
  std::array<std::uint32_t, 4> words{};
  zero.store_bits(words.data());
  check(words[0] == 0x80000000u);         // signed zero, not a float conversion
}

Definition at line 52 of file bits_body.h.

Here is the caller graph for this function:

◆ fma() [1/3]

template<::native::isa<> Arch>
requires (::native::avx512 <= Arch )

simd< fp16, 32, Arch > native::fma	(	simd< fp16, 32, Arch >	a,
		simd< fp16, 32, Arch >	b,
		simd< fp16, 32, Arch >	c )

inlineconstexprexportnoexcept

Compute a*b+c in each lane with one final half-precision rounding (VFMADD*PH). MXCSR rounding and exception controls apply, status flags may change, and DAZ/FTZ are ignored. Control bits are preserved; NaNs follow the instruction.

Definition at line 406 of file native.simd.ccm.

Here is the caller graph for this function:

◆ fma() [2/3]

template<::native::isa<> Arch>
requires (::native::avx512 <= Arch )

simd< fp16, 32, Arch > native::fma	(	simd< fp16, 32, Arch >	a,
		simd< fp16, 32, Arch >	b,
		simd< fp16, 32, Arch >	c )

inlineconstexprnoexcept

Compute a*b+c in each lane with one final half-precision rounding (VFMADD*PH). MXCSR rounding and exception controls apply, status flags may change, and DAZ/FTZ are ignored. Control bits are preserved; NaNs follow the instruction.

Definition at line 406 of file native.simd.ccm.

◆ fma() [3/3]

template<::native::isa<> Arch>
requires (::native::avx512 <= Arch )

simd< fp16, 8, Arch > native::fma	(	simd< fp16, 8, Arch >	a,
		simd< fp16, 8, Arch >	b,
		simd< fp16, 8, Arch >	c )

inlineconstexprexportnoexcept

Compute a*b+c in each lane with one final half-precision rounding (FMLA). The caller's FPCR rounding/FZ16/DN/exception controls apply, FPSR may change, and FPCR is preserved. NaN payload/sign follow the native instruction.

Definition at line 804 of file native.simd.ccm.

◆ load_simd() [1/2]

template<class V, class U, std::size_t A = 1, simd_access Access = simd_access::ordinary>
requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) && requires(U const
* p) { V::template load_memory<A>(p); }

V native::load_simd	(	U const *	p,
		simd_memory< A, Access >	= {} )

inlineconstexprnoexcept

Load all V::lanes elements using the element's memory customization.

Precondition: p addresses that many readable elements and meets alignment A. Exceptions propagate from the selected V::load_memory<A> operation.

Definition at line 40 of file common_body.h.

◆ load_simd() [2/2]

template<class V, simd_custom_element U, std::size_t A = 1, simd_access Access = simd_access::ordinary>
requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) && std::same_as
<typename V::value_type,typename simd_traits::storage_type>

V native::load_simd	(	U const *	p,
		simd_memory< A, Access >	= {} )

inlineconstexprnoexcept

Load custom elements through their typed memory operation, then project raw storage. The customization owns any normalization; this is not an arbitrary pointer cast.

Definition at line 49 of file common_body.h.

◆ load_simd_partial()

template<class V, class U, std::size_t A = 1, simd_access Access = simd_access::ordinary>
requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) &&
std::default_initializable && std::constructible_from<U,typename V::value_type &> && std::is_copy_assignable_v &&
requires(U const * p) { ::native::load_simd<V>(p); }

V native::load_simd_partial	(	U const *	p,
		std::size_t	count,
		typename V::value_type	fill = {},
		simd_memory< A, Access >	= {} )

inlineconstexprnoexcept

Load count elements and fill the remaining lanes with fill.

Precondition: count <= V::lanes; p may be null only when count == 0. Uses an element temporary; construction, assignment and loading may throw. The alignment hint does not extend the readable prefix.

Definition at line 96 of file common_body.h.

◆ log()

template<class R, std::size_t N>
requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_log(x); }

wide< R, N > native::log ( wide< R, N > const & input )

inlineconstexprnoexcept

Apply the element library's natural logarithm. Uses one array call when available, otherwise an elementwise fallback.

Definition at line 1130 of file wide.h.

◆ log1p()

template<class R, std::size_t N>
requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x)
{ detail::wide_generic_detail::adl_log1p(x); }

wide< R, N > native::log1p ( wide< R, N > const & input )

inlineconstexprnoexcept

Apply the element library's log(1+x) operation. Uses one array call when available, otherwise an elementwise fallback.

Definition at line 1172 of file wide.h.

◆ log2()

template<class R, std::size_t N>
requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_log2(x); }

wide< R, N > native::log2 ( wide< R, N > const & input )

inlineconstexprnoexcept

Apply the element library's base-two logarithm. Uses one array call when available, otherwise an elementwise fallback.

Definition at line 1151 of file wide.h.

◆ lzcnt()

template<isa< x86 > Arch = NATIVE_BASELINE>
requires (Arch.has(x86_feature::lzcnt))

std::uint16_t native::lzcnt ( std::uint16_t value )

inlineconstexprnoexcept

Export the LZCNT operation for unsigned 16-, 32- and 64-bit values. See the LZCNT group for the operation's feature and value contract.

Definition at line 24 of file lzcnt.h.

◆ mask_bits()

template<simd_mask_element M, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch )

auto native::mask_bits ( simd< M, N, Arch > m )

inlineconstexprnoexcept

Expand lane truth into unsigned integer zero/all-one words; preserve the lane count.

Definition at line 3289 of file simd_family.h.

◆ mask_cast()

template<class U, class T, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && simd_mask_element && simd_mask_element<T> && requires { typename simd<U,N,Arch>
::native_type; typename simd<T,N,Arch>::native_type; }

simd< U, N, Arch > native::mask_cast ( simd< T, N, Arch > value )

inlineconstexprnoexcept

Change full-mask lane width without changing lane truth or lane count.

Definition at line 805 of file simd_family.h.

◆ masked_add_zero()

template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> &&
::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)

simd< T, N, Arch > native::masked_add_zero	(	M	m,
		simd< T, N, Arch >	a,
		simd< T, N, Arch >	b )

inlineconstexprnoexcept

Add modulo the lane width in active lanes and zero inactive lanes.

Definition at line 3325 of file simd_family.h.

◆ masked_mul_zero()

template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> &&
::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)

simd< T, N, Arch > native::masked_mul_zero	(	M	m,
		simd< T, N, Arch >	a,
		simd< T, N, Arch >	b )

inlineconstexprnoexcept

Multiply modulo the lane width in active lanes and zero inactive lanes.

Definition at line 3367 of file simd_family.h.

◆ masked_scaleb()

template<std::size_t N, class M, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::native_scaleb_shape<N> &&(std::same_as<M,typename simd
<float,N,Arch>::mask_type> || std::same_as<M,typename simd<float,N,Arch>::vector_mask_type>)

simd< float, N, Arch > native::masked_scaleb	(	M	mask,
		simd< float, N, Arch >	prior,
		simd< float, N, Arch >	value,
		simd< float, N, Arch >	exponent )

inlineconstexprnoexcept

Scale active lanes by 2^floor(exponent), retaining prior in other lanes. Inactive lanes are excluded from the scaling operation. The result follows the caller's floating-point environment, including denormal controls. Available only for native AVX512F scaling shapes; packed widths below 16 require AVX512VL. No scalar, AVX2, NEON or Wasm software fallback exists.

Definition at line 4345 of file simd_family.h.

◆ masked_scaleb_zero()

template<std::size_t N, class M, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::native_scaleb_shape<N> &&(std::same_as<M,typename simd
<float,N,Arch>::mask_type> || std::same_as<M,typename simd<float,N,Arch>::vector_mask_type>)

simd< float, N, Arch > native::masked_scaleb_zero	(	M	mask,
		simd< float, N, Arch >	value,
		simd< float, N, Arch >	exponent )

inlineconstexprnoexcept

Scale active lanes by 2^floor(exponent), writing positive zero elsewhere.

Definition at line 4379 of file simd_family.h.

◆ masked_sub_zero()

template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> &&
::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)

simd< T, N, Arch > native::masked_sub_zero	(	M	m,
		simd< T, N, Arch >	a,
		simd< T, N, Arch >	b )

inlineconstexprnoexcept

Subtract modulo the lane width in active lanes and zero inactive lanes.

Definition at line 3346 of file simd_family.h.

◆ narrow_concat() [1/2]

template<simd_integer_element To, simd_integer_element From, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && (std::is_unsigned_v<To> && std::is_unsigned_v<From> && sizeof(From) == 2 * sizeof(To) &&
// The selected backend must implement this width. Complete storage alone // does not establish the arithmetic
instructions used by this operation. (N * sizeof(From) == 16 || N * sizeof(From) == 32 || (N * sizeof(From) == 64 &&
(sizeof(From) >= 4 || 1 != 0)) ) && requires { sizeof(simd<From, N, Arch>); sizeof(simd<To, 2 * N, Arch>); })

simd< To, 2 *N, Arch > native::narrow_concat	(	simd< From, N, Arch >	a,
		simd< From, N, Arch >	b )

inlineconstexprnoexcept

Truncate unsigned lanes to half their width and concatenate a then b. This preserves lane order and low bits; it does not saturate.

Definition at line 23 of file packing_body.h.

Here is the caller graph for this function:

◆ narrow_concat() [2/2]

template<simd_integer_element To, simd_integer_element From, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && (std::is_unsigned_v<To> && std::is_unsigned_v<From> && sizeof(From) == 2 * sizeof(To) &&
// The selected backend must implement this width. Complete storage alone // does not establish the arithmetic
instructions used by this operation. (N * sizeof(From) == 16 || N * sizeof(From) == 32 || (N * sizeof(From) == 64 &&
(sizeof(From) >= 4 || 1 != 0)) ) && requires { sizeof(simd<From, N, Arch>); sizeof(simd<To, 2 * N, Arch>); })

simd< To, 2 *N, Arch > native::narrow_concat	(	simd< From, N, Arch >	a,
		simd< From, N, Arch >	b )

inlineconstexprnoexcept

Truncate unsigned lanes to half their width and concatenate a then b. This preserves lane order and low bits; it does not saturate.

Definition at line 23 of file packing_body.h.

◆ observe_wasm_capabilities()

template<class V>
requires requires(V & validate,std::span<std::uint8_t const> bytes) { { validate(bytes) } noexcept -> std::same_as<std::optional
<bool>>; }

wasm_capabilities native::observe_wasm_capabilities ( V && validate )

constexprnoexcept

Query an embedder's validator without executing probe instructions. The nonthrowing callback accepts a byte span and returns optional<bool>: nullopt means unavailable/failed, false means observed absent. A valid empty module must first be accepted. Feature queries then proceed independently. The callback translates engine errors into nullopt; no loader is selected.

Definition at line 84 of file features.h.

◆ operator!=() [1/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator!=	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator!=() [2/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator!=	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ operator%() [1/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator%	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator%() [2/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator%	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ operator%=() [1/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator%=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator%=() [2/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator%=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ operator&()

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator&	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator&=() [1/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator&=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator&=() [2/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator&=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ operator*() [1/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator*	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator*() [2/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator*	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ operator*=() [1/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator*=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator*=() [2/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator*=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ operator+()

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator+	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator+=() [1/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator+=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator+=() [2/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator+=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ operator-() [1/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator-	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator-() [2/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator-	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ operator-=() [1/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator-=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator-=() [2/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator-=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ operator/() [1/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator/	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator/() [2/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator/	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ operator/=() [1/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator/=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator/=() [2/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator/=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ operator<<()

template<simd_integer_element T, std::size_t N, std::size_t K, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && (K >= sizeof(T) * 8)

void native::operator<<	(	simd< T, N, Arch >	a,
		imm_t< K >	)

delete

Reject this unsupported operand combination instead of converting implicitly to a native register.

Shift integer lanes left, reducing the count modulo the lane width.

Shift every lane left by K bits, discarding high bits. Require K smaller than the lane bit width.

Definition at line 2358 of file simd_family.h.

◆ operator==() [1/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator==	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator==() [2/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator==	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ operator>()

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator>	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator>=()

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator>=	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator>>() [1/3]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator>>	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator>>() [2/3]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator>>	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ operator>>() [3/3]

template<simd_integer_element T, std::size_t N, std::size_t K, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && (K >= sizeof(T) * 8)

void native::operator>>	(	simd< T, N, Arch >	a,
		imm_t< K >	)

delete

Reject this unsupported operand combination instead of converting implicitly to a native register.

Shift integer lanes right, extending signed lanes and reducing the count modulo their width.

Shift every lane right by K; signed lanes extend the sign, unsigned lanes shift in zero. Require K smaller than the lane bit width.

Definition at line 2364 of file simd_family.h.

◆ operator>>=() [1/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator>>=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator>>=() [2/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator>>=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ operator^() [1/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator^	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator^() [2/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator^	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ operator^=() [1/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator^=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator^=() [2/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator^=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ operator|() [1/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator\|	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator|() [2/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator\|	(	simd< T, N, A >	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ operator|=() [1/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator\|=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Here is the caller graph for this function:

◆ operator|=() [2/2]

template<class T, class U, std::size_t N, std::size_t M, isa<> A, isa<> B>
requires (A!=B || (N!=M && (N==2 || N==3 || M==2 || M==3)))

void native::operator\|=	(	simd< T, N, A > &	,
		simd< U, M, B >	)

delete

Make the corresponding native overload set visible through this module.

Reject mixed architectures and mismatched short-vector widths before native conversions can participate.

Make the corresponding native overload set visible through this module.

Here is the caller graph for this function:

◆ pairwise_add_widened() [1/2]

template<simd_integer_element T, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && (std::is_unsigned_v<T> && sizeof(T) <= 4 && N > 1 && N % 2 == 0 &&
detail::integer_arithmetic<T,N,Arch>)

auto native::pairwise_add_widened ( simd< T, N, Arch > value )

inlineconstexprnoexcept

Sum adjacent unsigned lanes into lanes twice as wide. No sum can overflow. The result contains half as many lanes; full-register inputs keep their width.

Definition at line 36 of file integer_body.h.

Here is the caller graph for this function:

◆ pairwise_add_widened() [2/2]

template<simd_integer_element T, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && (std::is_unsigned_v<T> && sizeof(T) <= 4 && N > 1 && N % 2 == 0 &&
detail::integer_arithmetic<T,N,Arch>)

auto native::pairwise_add_widened ( simd< T, N, Arch > value )

inlineconstexprnoexcept

Sum adjacent unsigned lanes into lanes twice as wide. No sum can overflow. The result contains half as many lanes; full-register inputs keep their width.

Definition at line 36 of file integer_body.h.

◆ popcnt()

template<isa< x86 > Arch = NATIVE_BASELINE>
requires (Arch.has(x86_feature::popcnt))

std::uint16_t native::popcnt ( std::uint16_t value )

inlineconstexprnoexcept

Export the POPCNT operation for unsigned 16-, 32- and 64-bit values. See the POPCNT group for the operation's feature and value contract.

Definition at line 24 of file popcnt.h.

◆ popcount() [1/2]

template<simd_integer_element T, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && (std::is_unsigned_v<T> && detail::integer_arithmetic<T,N,Arch>)

simd< T, N, Arch > native::popcount ( simd< T, N, Arch > value )

inlineconstexprnoexcept

Count set bits independently in each unsigned integer lane. Byte populations use CNT on NEON and register nibble tables on x86.

Definition at line 96 of file integer_body.h.

Here is the caller graph for this function:

◆ popcount() [2/2]

template<simd_integer_element T, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && (std::is_unsigned_v<T> && detail::integer_arithmetic<T,N,Arch>)

simd< T, N, Arch > native::popcount ( simd< T, N, Arch > value )

inlineconstexprnoexcept

Count set bits independently in each unsigned integer lane. Byte populations use CNT on NEON and register nibble tables on x86.

Definition at line 96 of file integer_body.h.

◆ reduce_add_widened() [1/2]

template<simd_integer_element T, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && (std::is_unsigned_v<T> && sizeof(T)<=4 && detail::integer_arithmetic<T,N,Arch>)

std::uint64_t native::reduce_add_widened ( simd< T, N, Arch > value )

inlineconstexprnoexcept

Sum unsigned 8-, 16-, or 32-bit lanes exactly into a 64-bit scalar. Reduction widens before adding: it never wraps at the input lane width.

Definition at line 168 of file integer_body.h.

Here is the caller graph for this function:

◆ reduce_add_widened() [2/2]

template<simd_integer_element T, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && (std::is_unsigned_v<T> && sizeof(T)<=4 && detail::integer_arithmetic<T,N,Arch>)

std::uint64_t native::reduce_add_widened ( simd< T, N, Arch > value )

inlineconstexprnoexcept

Sum unsigned 8-, 16-, or 32-bit lanes exactly into a 64-bit scalar. Reduction widens before adding: it never wraps at the input lane width.

Definition at line 168 of file integer_body.h.

◆ reinterpret_bits() [1/2]

template<simd_integer_element To, simd_integer_element From, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && (sizeof(From) * N % sizeof(To) == 0 && requires { typename simd<From,N,Arch>::native_type;
typename simd<To,sizeof(From)*N/sizeof(To),Arch>::native_type; } && sizeof(typename simd<From,N,Arch>::native_type)
== sizeof(typename simd<To,sizeof(From)*N/sizeof(To),Arch>::native_type) && (sizeof(typename simd<From,N,Arch>
::native_type) <= 16 || sizeof(typename simd<From,N,Arch>::native_type) == 32 || sizeof(typename simd<From,N,Arch>
::native_type) == 64 ))

auto native::reinterpret_bits ( simd< From, N, Arch > value ) -> simd< To, sizeof(From) *N/sizeof(To), Arch >

inlineconstexprnoexcept

Repartition the bits of an integer register without conversion or a spill. Both shapes need equal physical storage sizes supported by this backend's target. Storage-only element views are allowed; lane arithmetic is not required.

Definition at line 23 of file integer_body.h.

Here is the caller graph for this function:

◆ reinterpret_bits() [2/2]

template<simd_integer_element To, simd_integer_element From, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && (sizeof(From) * N % sizeof(To) == 0 && requires { typename simd<From,N,Arch>::native_type;
typename simd<To,sizeof(From)*N/sizeof(To),Arch>::native_type; } && sizeof(typename simd<From,N,Arch>::native_type)
== sizeof(typename simd<To,sizeof(From)*N/sizeof(To),Arch>::native_type) && (sizeof(typename simd<From,N,Arch>
::native_type) <= 16 || sizeof(typename simd<From,N,Arch>::native_type) == 32 || sizeof(typename simd<From,N,Arch>
::native_type) == 64 ))

auto native::reinterpret_bits ( simd< From, N, Arch > value ) -> simd< To, sizeof(From) *N/sizeof(To), Arch >

inlineconstexprnoexcept

Repartition the bits of an integer register without conversion or a spill. Both shapes need equal physical storage sizes supported by this backend's target. Storage-only element views are allowed; lane arithmetic is not required.

Definition at line 23 of file integer_body.h.

◆ rorx() [1/2]

template<unsigned Imm8, isa< x86 > Arch = NATIVE_BASELINE>
requires (Arch.has(x86_feature::bmi2) && Imm8 <= 255)

std::uint32_t native::rorx ( std::uint32_t value )

inlineconstexprexportnoexcept

Rotate using the module baseline, or an explicitly supplied ISA. rorx<Arch, Imm8> also selects an explicit architecture.

Definition at line 100 of file native.x86.bmi2.ccm.

Here is the caller graph for this function:

◆ rorx() [2/2]

template<unsigned Imm8, isa< x86 > Arch = NATIVE_BASELINE>
requires (Arch.has(x86_feature::bmi2) && Imm8 <= 255)

std::uint64_t native::rorx ( std::uint64_t value )

inlineconstexprexportnoexcept

Rotate using the module baseline, or an explicitly supplied ISA. rorx<Arch, Imm8> also selects an explicit architecture.

Definition at line 109 of file native.x86.bmi2.ccm.

◆ scaleb()

template<std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::native_scaleb_shape<N>

simd< float, N, Arch > native::scaleb	(	simd< float, N, Arch >	value,
		simd< float, N, Arch >	exponent )

inlineconstexprnoexcept

Scale every lane by 2^floor(exponent), including fractional exponents. Unlike an integer ldexp exponent, the exponent argument is itself a vector.

Definition at line 4399 of file simd_family.h.

◆ scalef() [1/2]

template double native::scalef	(	double	,
		double	)

noexcept

Scale by a power of two after truncating the exponent toward zero.

See also: scalef

◆ scalef() [2/2]

template float native::scalef	(	float	,
		float	)

noexcept

Scale by a power of two after truncating the exponent toward zero.

See also: scalef

◆ select()

template<simd_integer_element T, std::size_t N, class M, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) &&(::native::detail::avx512_backend::integer_shape<T, N> &&
::native::detail::avx512_backend::integer_mask_for<M, T, N, Arch>)

simd< T, N, Arch > native::select	(	M	m,
		simd< T, N, Arch >	a,
		simd< T, N, Arch >	b )

inlineconstexprnoexcept

Choose a in true lanes and b in false lanes; both operands are evaluated.

Definition at line 3250 of file simd_family.h.

◆ sin()

template<class R, std::size_t N>
requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_sin(x); }

wide< R, N > native::sin ( wide< R, N > const & input )

inlineconstexprnoexcept

Apply the element library's sine operation in radians. Uses one array call when available, otherwise an elementwise fallback.

Definition at line 1003 of file wide.h.

◆ sincos()

template<class R, std::size_t N>
requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x)
{ detail::wide_generic_detail::adl_sincos(x); }

auto native::sincos ( wide< R, N > const & input )

inlineconstexprnoexcept

Return paired sine and cosine packs using the element's paired operation. Uses one array call when available, otherwise an elementwise fallback.

Definition at line 1263 of file wide.h.

◆ store_simd() [1/2]

template<simd_custom_element U, class V, std::size_t A = 1, simd_access Access = simd_access::ordinary>
requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) && std::same_as
<typename V::value_type,typename simd_traits::storage_type>

void native::store_simd	(	U *	p,
		V	value,
		simd_memory< A, Access >	= {} )

inlineconstexprnoexcept

Convert raw storage to the custom element vector before its typed store. Construction and storage both contribute to the exception specification.

Definition at line 67 of file common_body.h.

◆ store_simd() [2/2]

template<class U, class V, std::size_t A = 1, simd_access Access = simd_access::ordinary>
requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) && requires(V value,U
* p) { value.template store_memory<A>(p); }

void native::store_simd	(	U *	p,
		V	value,
		simd_memory< A, Access >	= {} )

inlineconstexprnoexcept

Store all logical lanes using the element's memory customization.

Precondition: p addresses that many writable elements and meets alignment A.

Definition at line 58 of file common_body.h.

◆ store_simd_partial()

template<class U, class V, std::size_t A = 1, simd_access Access = simd_access::ordinary>
requires detail::memory_architecture<V,U>::known && NATIVE_COMMON_ARCH(detail::memory_architecture_v<V,U>) &&
std::default_initializable && std::is_copy_assignable_v && requires(U * p,V value) { ::native::store_simd(p,value); }

void native::store_simd_partial	(	U *	p,
		V	value,
		std::size_t	count,
		simd_memory< A, Access >	= {} )

inlineconstexprnoexcept

Store the first count logical lanes, leaving the following memory alone.

Precondition: count <= V::lanes; p may be null only when count == 0. Element construction, assignment and storage determine the exception guarantee.

Definition at line 112 of file common_body.h.

◆ tanh()

template<class R, std::size_t N>
requires (::native::detail::wide_target<R> == NATIVE_WIDE_INDEX) && requires(R const & x) { detail::wide_generic_detail::adl_tanh(x); }

wide< R, N > native::tanh ( wide< R, N > const & input )

inlineconstexprnoexcept

Apply the element library's hyperbolic tangent. Uses one array call when available, otherwise an elementwise fallback.

Definition at line 1193 of file wide.h.

◆ target_features() [1/2]

template<architecture Family = target_arch>

isa< Family > native::target_features ( std::string_view text )

constexprnoexcept

Parse registered target features for one family, defaulting to the compiler target. CPU names, negative features and unknown or foreign features produce an invalid set.

Definition at line 561 of file isa.h.

Here is the caller graph for this function:

◆ target_features() [2/2]

template<architecture Family = target_arch>

isa< Family > native::target_features ( std::string_view text )

constexprnoexcept

Parse registered target features for one family, defaulting to the compiler target. CPU names, negative features and unknown or foreign features produce an invalid set.

Definition at line 561 of file isa.h.

◆ to_predicate()

template<class T, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && simd_mask_element<T> && ::native::detail::avx512_backend::predicate_shape<N> && requires
{ typename simd<T,N,Arch>::native_type; }

predicate< N, Arch > native::to_predicate ( simd< T, N, Arch > value )

inlineconstexprnoexcept

Compress full-vector truth into a supported compact predicate.

Definition at line 812 of file simd_family.h.

◆ to_vector_mask()

template<class T, std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && simd_mask_element<T> && ::native::detail::avx512_backend::predicate_shape<N> && requires
{ typename simd<T,N,Arch>::native_type; }

simd< T, N, Arch > native::to_vector_mask ( predicate< N, Arch > value )

inlineconstexprnoexcept

Expand a predicate to canonical zero/all-one lanes of mask element T.

Definition at line 834 of file simd_family.h.

◆ trunc()

template<std::size_t N, ::native::isa<> Arch>
requires (::native::avx512 <= Arch ) && ::native::detail::avx512_backend::float_shape<N>

simd< float, N, Arch > native::trunc ( simd< float, N, Arch > x )

inlineconstexprnoexcept

Round each lane toward zero, independently of ambient rounding. Signed zeros and infinities are preserved; NaNs remain NaNs. Raw denormal handling still follows the CPU environment. No NaN payload or FP-status promise is added.

template<native::isa<> Arch>
void rounding() {
  using V = native::simd<float, 4, Arch>;
  V x{-1.75f, -0.25f, 0.25f, 1.75f};
  check(all(native::floor(x) == V{-2.f, -1.f, 0.f, 1.f}));
  check(all(native::ceil(x) == V{-1.f, -0.f, 1.f, 2.f}));
  check(all(native::trunc(x) == V{-1.f, -0.f, 0.f, 1.f}));
}

Definition at line 5174 of file simd_family.h.

◆ trunc_sat()

template<simd_integer_element To, std::floating_point From, std::size_t N, isa<> A>
requires (A.has(wasm_feature::simd128)) && (sizeof(From) * N == 16 && sizeof(To) == 4)

simd< To, 4, A > native::trunc_sat ( simd< From, N, A > a )

inlineconstexprnoexcept

Saturating floating-to-integer conversion; NaN becomes zero. Binary64 leaves the upper two result lanes zero.

Definition at line 7098 of file simd_family.h.

Here is the caller graph for this function:

◆ wasm_feature_probe()

std::span< std::uint8_t const > native::wasm_feature_probe ( wasm_feature feature )

constexprnoexcept

A complete module for validating one feature, without executing it. The returned immutable bytes have static lifetime; unknown enums give an empty span. Validation must use the settings of the intended runtime.

Definition at line 31 of file features.h.

Variable Documentation

◆ atan2_width [1/2]

template<class T, std::size_t K, isa A = NATIVE_BASELINE>

std::size_t native::atan2_width

inlineconstexpr

Recommended independent register count for atan2's two-input kernel. Small batches limit the live values used by classification and quadrants.

Definition at line 76 of file wide_math.h.

◆ atan2_width [2/2]

template<class T, std::size_t K, isa A = NATIVE_BASELINE>

std::size_t native::atan2_width = detail::math_branching_width<T, K, A>

inlineconstexpr

Recommended independent register count for atan2's two-input kernel. Small batches limit the live values used by classification and quadrants.

Definition at line 76 of file wide_math.h.

◆ exp_width [1/2]

template<class T, std::size_t K, isa A = NATIVE_BASELINE>

std::size_t native::exp_width

inlineconstexpr

Recommended independent register count for degree-six exp on simd<T,K,A>. A defaults to the defining header or module's compiler baseline. This is tuning advice, not an instruction-availability test or a guaranteed optimum.

Definition at line 38 of file wide_math.h.

◆ exp_width [2/2]

template<class T, std::size_t K, isa A = NATIVE_BASELINE>

std::size_t native::exp_width

inlineconstexpr

Initial value:

                                       = [] {
  if constexpr (!detail::math_vector_shape<T, K, A>) return std::size_t{1};
  else if constexpr (A.family == wasm) return std::size_t{2};
  else if constexpr (A.family == x86 && K >= 8) return std::size_t{6};
  else return std::size_t{4};
}()

Recommended independent register count for degree-six exp on simd<T,K,A>. A defaults to the defining header or module's compiler baseline. This is tuning advice, not an instruction-availability test or a guaranteed optimum.

Definition at line 38 of file wide_math.h.

◆ imm [1/3]

template<std::size_t K>

imm_t<K> native::imm

inlineconstexpr

The value form of an immediate: for example, broadcast(v, native::imm<1>).

Definition at line 82 of file common.h.

◆ imm [2/3]

template<std::size_t K>

imm_t<K> native::imm

inlineconstexpr

The value form of an immediate: for example, broadcast(v, native::imm<1>).

Definition at line 82 of file common.h.

◆ imm [3/3]

template<std::size_t K>

imm_t<K> native::imm

inlineconstexpr

The value form of an immediate: for example, broadcast(v, native::imm<1>).

Definition at line 82 of file common.h.

Classes

Concepts

Typedefs

Enumerations

Functions

Variables

Detailed Description

Enumeration Type Documentation

◆ cpu_vendor

◆ simd_access [1/2]

◆ simd_access [2/2]

Function Documentation

◆ abs()

◆ atan2()

◆ ceil()

◆ classify_isa() [1/6]

◆ classify_isa() [2/6]

◆ classify_isa() [3/6]

◆ classify_isa() [4/6]

◆ classify_isa() [5/6]

◆ classify_isa() [6/6]

◆ compress()

◆ compress_store()

◆ convert() [1/2]

◆ convert() [2/2]

◆ cos()

◆ cvtss_sh()

◆ damping_gain()

◆ decode_wasm_capabilities()

◆ dot2() [1/2]

◆ dot2() [2/2]

◆ exp()

◆ exp2()

◆ expand()

◆ expm1()

◆ fast_to_bf16()

◆ feature_closure() [1/2]

◆ feature_closure() [2/2]

◆ floor()

◆ flush_to_zero()

◆ fma() [1/3]

◆ fma() [2/3]

◆ fma() [3/3]

◆ load_simd() [1/2]

◆ load_simd() [2/2]

◆ load_simd_partial()

◆ log()

◆ log1p()

◆ log2()

◆ lzcnt()

◆ mask_bits()

◆ mask_cast()

◆ masked_add_zero()

◆ masked_mul_zero()

◆ masked_scaleb()

◆ masked_scaleb_zero()

◆ masked_sub_zero()

◆ narrow_concat() [1/2]

◆ narrow_concat() [2/2]

◆ observe_wasm_capabilities()

◆ operator!=() [1/2]

◆ operator!=() [2/2]

◆ operator%() [1/2]

◆ operator%() [2/2]

◆ operator%=() [1/2]

◆ operator%=() [2/2]

◆ operator&()

◆ operator&=() [1/2]

◆ operator&=() [2/2]

◆ operator*() [1/2]

◆ operator*() [2/2]

◆ operator*=() [1/2]

◆ operator*=() [2/2]

◆ operator+()

◆ operator+=() [1/2]

◆ operator+=() [2/2]

◆ operator-() [1/2]

◆ operator-() [2/2]

◆ operator-=() [1/2]

◆ operator-=() [2/2]