BMI2

Collaboration diagram for BMI2:

Functions
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	native::bzhi (std::uint32_t value, unsigned index) noexcept
	Zero bits at and above index's low eight bits; an index at least the width leaves value unchanged.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint64_t	native::bzhi (std::uint64_t value, unsigned index) noexcept
	BZHI with a 64-bit value and the same low-eight-bit index semantics.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	native::mulx (std::uint32_t a, std::uint32_t b, std::uint32_t *high) noexcept
	Return the low product and write the high product to a valid output pointer.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint64_t	native::mulx (std::uint64_t a, std::uint64_t b, std::uint64_t *high) noexcept
	Return the low 64 bits and write the high 64 bits of the unsigned 128-bit product.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	native::pdep (std::uint32_t value, std::uint32_t maskmask) noexcept
	Parallel bit deposit (PDEP): place the low popcount(mask) bits into mask's set positions, in order.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint64_t	native::pdep (std::uint64_t value, std::uint64_t maskmask) noexcept
	Parallel bit deposit (PDEP), with 64-bit operands.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	native::pext (std::uint32_t value, std::uint32_t maskmask) noexcept
	Parallel bit extract (PEXT): gather mask's selected bits into the low bits, in order.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint64_t	native::pext (std::uint64_t value, std::uint64_t maskmask) noexcept
	Parallel bit extract (PEXT), with 64-bit operands.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	native::shlx (std::uint32_t value, unsigned count) noexcept
	Logical left shift using the low five bits of count.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint64_t	native::shlx (std::uint64_t value, unsigned count) noexcept
	Logical left shift using the low six bits of count.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint32_t	native::shrx (std::uint32_t value, unsigned count) noexcept
	Logical right shift using the low five bits of count.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::uint64_t	native::shrx (std::uint64_t value, unsigned count) noexcept
	Logical right shift using the low six bits of count.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::int32_t	native::sarx (std::int32_t value, unsigned count) noexcept
	Arithmetic right shift using the low five bits of count, propagating the sign bit.
template<isa< x86 > Arch = NATIVE_BASELINE> requires (Arch.has(x86_feature::bmi2))
constexpr std::int64_t	native::sarx (std::int64_t value, unsigned count) noexcept
	Arithmetic right shift using the low six bits of count, propagating the sign bit.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::bmi2) && Imm8 <= 255)
constexpr std::uint32_t	native::rorx (std::uint32_t value) noexcept
	Rotate right by an immediate byte; the low five bits select the 32-bit rotation.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::bmi2) && Imm8 <= 255)
constexpr std::uint64_t	native::rorx (std::uint64_t value) noexcept
	Rotate right by an immediate byte; the low six bits select the 64-bit rotation.

Detailed Description

Integer bit manipulation; runtime calls require exactly x86_feature::bmi2. Constant evaluation supports every x86 Arch; weak tags select consteval overloads.