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native 0.0.1
Vectors, masks and wide register packs for C++26
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Functions | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sm4)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sm4e (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept |
| Perform four SM4 data rounds with state words and successive round keys in ascending lanes. | |
| template<isa< arm > Arch> requires (Arch.has(arm_feature::sm4)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sm4ekey (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept |
Individual Advanced SIMD operations on four native-order uint32_t words. Runtime calls require the named instruction feature; the compiler's "sm4" target enables both SM3 and SM4. Admit target_features<arm>("sm4") before entering its compiled leaf. These operations do not modify FPCR, FPSR or NZCV. Feature-absent overloads are immediate-only and require NEON vector storage.
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inlineconstexprexportnoexcept |
Perform four SM4 key-schedule rounds with state words and successive constants in ascending lanes.
Definition at line 112 of file native.arm.sm4.ccm.