native.x86.f16c.ccm

// SPDX-License-Identifier: BSD-2-Clause OR Apache-2.0
module;
#include "native/isa_import.h"
#include "native/x86/f16c.h"
#include "native/detail/constexpr_float.h"
#include "native/targets.h"
export module native.x86.f16c;
export import native.x86.features;
export import native.simd;
// SPDX-License-Identifier: BSD-2-Clause OR Apache-2.0
#if NATIVE_HOST_X86 || defined(NATIVE_DOXYGEN)
namespace native::detail {
  template<unsigned Imm8> constexpr auto f16c_rounding() noexcept {
    using r=constexpr_float::rounding;
    if constexpr(Imm8&4) return r::nearest_even;
    else if constexpr((Imm8&3)==1) return r::downward;
    else if constexpr((Imm8&3)==2) return r::upward;
    else if constexpr((Imm8&3)==3) return r::toward_zero;
    else return r::nearest_even;
  }
  template<isa<x86> Arch,unsigned Imm8,std::size_t N>
  consteval simd<fp16,N,Arch> f16c_narrow(simd<float,N,Arch> input) noexcept {
    std::array<float,N> values{};input.store(values.data());
    auto source=std::bit_cast<std::array<std::uint32_t,N>>(values);
    std::array<std::uint16_t,N> result{};
    for(std::size_t i=0;i<N;++i) result[i]=constexpr_float::convert_bits<
      constexpr_float::binary16,constexpr_float::binary32>(source[i],f16c_rounding<Imm8>());
    return simd<fp16,N,Arch>::load_bits(result.data());
  }
  template<isa<x86> Arch,std::size_t N>
  consteval simd<float,N,Arch> f16c_widen(simd<fp16,N,Arch> input) noexcept {
    std::array<std::uint16_t,N> source{};
    std::array<std::uint32_t,N> result{};
    input.store_bits(source.data());
    for(std::size_t i=0;i<N;++i) result[i]=constexpr_float::convert_bits<
      constexpr_float::binary32,constexpr_float::binary16>(source[i]);
    auto values=std::bit_cast<std::array<float,N>>(result);
    return simd<float,N,Arch>::load(values.data());
  }
}
export namespace native {

  template<isa<x86> Arch, unsigned Imm8>
    requires(Arch.has(x86_feature::f16c) && Imm8 <= 255)
  native_nodiscard native_inline native_target("f16c") constexpr
  simd<fp16, 4, Arch> cvtps_ph(simd<float, 4, Arch> a) noexcept {
    if consteval { return detail::f16c_narrow<Arch,Imm8>(a); } else {
      // VCVTPS2PH zeroes the unused high half of its destination.
      return simd<fp16, 4, Arch>::from_native(
        detail::x86_f16c::cvtps_ph<Arch, Imm8>(a.to_native()));
    }
  }

  template<isa<x86> Arch, unsigned Imm8>
    requires(requires { sizeof(simd<float,4,Arch>); sizeof(simd<fp16,4,Arch>); } && !Arch.has(x86_feature::f16c) && Imm8 <= 255)
  native_nodiscard consteval
  simd<fp16, 4, Arch> cvtps_ph(simd<float, 4, Arch> a) noexcept {
    return detail::f16c_narrow<Arch,Imm8>(a);
  }

  template<isa<x86> Arch, unsigned Imm8>
    requires(Arch.has(x86_feature::f16c) && Imm8 <= 255)
  native_nodiscard native_inline native_target("f16c") constexpr
  simd<fp16, 8, Arch> cvtps_ph(simd<float, 8, Arch> a) noexcept {
    if consteval { return detail::f16c_narrow<Arch,Imm8>(a); } else {
      return simd<fp16, 8, Arch>::from_native(
        detail::x86_f16c::cvtps_ph<Arch, Imm8>(a.to_native()));
    }
  }

  template<isa<x86> Arch, unsigned Imm8>
    requires(requires { sizeof(simd<float,8,Arch>); sizeof(simd<fp16,8,Arch>); } && !Arch.has(x86_feature::f16c) && Imm8 <= 255)
  native_nodiscard consteval
  simd<fp16, 8, Arch> cvtps_ph(simd<float, 8, Arch> a) noexcept {
    return detail::f16c_narrow<Arch,Imm8>(a);
  }

  template<isa<x86> Arch, unsigned Lanes>
    requires(Arch.has(x86_feature::f16c) && Lanes == 4)
  native_nodiscard native_inline native_target("f16c") constexpr
  simd<float, 4, Arch> cvtph_ps(simd<fp16, 4, Arch> a) noexcept {
    if consteval { return detail::f16c_widen<Arch>(a); } else {
      return simd<float, 4, Arch>::from_native(
        detail::x86_f16c::cvtph_ps<Arch, 4>(a.to_native()));
    }
  }

  template<isa<x86> Arch, unsigned Lanes>
    requires(requires { sizeof(simd<float,4,Arch>); sizeof(simd<fp16,4,Arch>); } && !Arch.has(x86_feature::f16c) && Lanes == 4)
  native_nodiscard consteval
  simd<float, 4, Arch> cvtph_ps(simd<fp16, 4, Arch> a) noexcept {
    return detail::f16c_widen<Arch>(a);
  }

  template<isa<x86> Arch, unsigned Lanes>
    requires(Arch.has(x86_feature::f16c) && Lanes == 8)
  native_nodiscard native_inline native_target("f16c") constexpr
  simd<float, 8, Arch> cvtph_ps(simd<fp16, 8, Arch> a) noexcept {
    if consteval { return detail::f16c_widen<Arch>(a); } else {
      return simd<float, 8, Arch>::from_native(
        detail::x86_f16c::cvtph_ps<Arch, 8>(a.to_native()));
    }
  }

  template<isa<x86> Arch, unsigned Lanes>
    requires(requires { sizeof(simd<float,8,Arch>); sizeof(simd<fp16,8,Arch>); } && !Arch.has(x86_feature::f16c) && Lanes == 8)
  native_nodiscard consteval
  simd<float, 8, Arch> cvtph_ps(simd<fp16, 8, Arch> a) noexcept {
    return detail::f16c_widen<Arch>(a);
  }

  template<isa<x86> Arch, unsigned Imm8>
    requires(Arch.has(x86_feature::f16c) && Imm8 <= 255)
  native_nodiscard native_inline native_target("f16c") constexpr
  std::uint16_t cvtss_sh(float a) noexcept {
    if consteval { return detail::constexpr_float::convert_bits<detail::constexpr_float::binary16,
      detail::constexpr_float::binary32>(std::bit_cast<std::uint32_t>(a),detail::f16c_rounding<Imm8>()); } else {
      return detail::x86_f16c::cvtss_sh<Arch, Imm8>(a);
    }
  }

  template<isa<x86> Arch, unsigned Imm8>
    requires(!Arch.has(x86_feature::f16c) && Imm8 <= 255)
  native_nodiscard consteval
  std::uint16_t cvtss_sh(float a) noexcept {
    return detail::constexpr_float::convert_bits<detail::constexpr_float::binary16,
      detail::constexpr_float::binary32>(std::bit_cast<std::uint32_t>(a),detail::f16c_rounding<Imm8>());
  }

  template<unsigned Imm8, isa<x86> Arch = NATIVE_BASELINE>
    requires(Arch.has(x86_feature::f16c) && Imm8 <= 255)
  native_nodiscard native_inline native_target("f16c") constexpr
  std::uint16_t cvtss_sh(float a) noexcept {
    if consteval { return detail::constexpr_float::convert_bits<detail::constexpr_float::binary16,
      detail::constexpr_float::binary32>(std::bit_cast<std::uint32_t>(a),detail::f16c_rounding<Imm8>()); } else {
      return cvtss_sh<Arch, Imm8>(a);
    }
  }

  template<unsigned Imm8, isa<x86> Arch = NATIVE_BASELINE>
    requires(!Arch.has(x86_feature::f16c) && Imm8 <= 255)
  native_nodiscard consteval
  std::uint16_t cvtss_sh(float a) noexcept {
    return detail::constexpr_float::convert_bits<detail::constexpr_float::binary16,
      detail::constexpr_float::binary32>(std::bit_cast<std::uint32_t>(a),detail::f16c_rounding<Imm8>());
  }

  template<isa<x86> Arch = NATIVE_BASELINE> requires(Arch.has(x86_feature::f16c))
  native_nodiscard native_inline native_target("f16c") constexpr
  float cvtsh_ss(std::uint16_t a) noexcept {
    if consteval { return std::bit_cast<float>(detail::constexpr_float::convert_bits<
      detail::constexpr_float::binary32,detail::constexpr_float::binary16>(a)); } else {
      return detail::x86_f16c::cvtsh_ss<Arch>(a);
    }
  }

  template<isa<x86> Arch = NATIVE_BASELINE> requires(!Arch.has(x86_feature::f16c))
  native_nodiscard consteval
  float cvtsh_ss(std::uint16_t a) noexcept {
    return std::bit_cast<float>(detail::constexpr_float::convert_bits<
      detail::constexpr_float::binary32,detail::constexpr_float::binary16>(a));
  }

  template<isa<x86> Arch, unsigned Imm8, class V> void cvtps_ph(V) = delete;
  template<isa<x86> Arch, unsigned Lanes, class V> void cvtph_ps(V) = delete;
}
#endif