- Generated by
1.18.0
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native 0.0.1
Vectors, masks and wide register packs for C++26
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Functions | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha1)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sha1c (simd< std::uint32_t, 4, Arch > abcd, std::uint32_t e, simd< std::uint32_t, 4, Arch > wk) noexcept |
| Perform four SHA-1 rounds using choice; wk already includes the round constants. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha1)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sha1p (simd< std::uint32_t, 4, Arch > abcd, std::uint32_t e, simd< std::uint32_t, 4, Arch > wk) noexcept |
| Perform four SHA-1 rounds using parity; wk already includes the round constants. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha1)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sha1m (simd< std::uint32_t, 4, Arch > abcd, std::uint32_t e, simd< std::uint32_t, 4, Arch > wk) noexcept |
| Perform four SHA-1 rounds using majority; wk already includes the round constants. | |
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template<isa< arm > Arch = NATIVE_BASELINE> requires (Arch.has(arm_feature::sha1)) | |
| constexpr std::uint32_t | native::sha1h (std::uint32_t a) noexcept |
| Rotate a SHA-1 state word right by two bits; Arch defaults to the module baseline. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha1)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sha1su0 (simd< std::uint32_t, 4, Arch > w0_3, simd< std::uint32_t, 4, Arch > w4_7, simd< std::uint32_t, 4, Arch > w8_11) noexcept |
| Compute the first part of the SHA-1 schedule update for four consecutive words. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha1)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sha1su1 (simd< std::uint32_t, 4, Arch > partial, simd< std::uint32_t, 4, Arch > w12_15) noexcept |
| Finish the four-word SHA-1 schedule update from sha1su0 and words 12 through 15. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha2)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sha256h (simd< std::uint32_t, 4, Arch > abcd, simd< std::uint32_t, 4, Arch > efgh, simd< std::uint32_t, 4, Arch > wk) noexcept |
| Return a,b,c,d after four SHA-256 rounds; wk includes round constants. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha2)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sha256h2 (simd< std::uint32_t, 4, Arch > efgh, simd< std::uint32_t, 4, Arch > abcd, simd< std::uint32_t, 4, Arch > wk) noexcept |
| Return e,f,g,h after four SHA-256 rounds; abcd is the state before those rounds. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha2)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sha256su0 (simd< std::uint32_t, 4, Arch > w0_3, simd< std::uint32_t, 4, Arch > w4_7) noexcept |
| Compute the first part of a four-word SHA-256 schedule update. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha2)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sha256su1 (simd< std::uint32_t, 4, Arch > partial, simd< std::uint32_t, 4, Arch > w8_11, simd< std::uint32_t, 4, Arch > w12_15) noexcept |
| Finish the four-word SHA-256 schedule update from sha256su0. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha512)) | |
| constexpr simd< std::uint64_t, 2, Arch > | native::sha512h (simd< std::uint64_t, 2, Arch > sum, simd< std::uint64_t, 2, Arch > fg, simd< std::uint64_t, 2, Arch > de) noexcept |
| Apply SHA512H to prepared round sums and packed f,g and d,e state. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha512)) | |
| constexpr simd< std::uint64_t, 2, Arch > | native::sha512h2 (simd< std::uint64_t, 2, Arch > sum_ab, simd< std::uint64_t, 2, Arch > c_, simd< std::uint64_t, 2, Arch > ab) noexcept |
| Apply SHA512H2 to prepared sums, c, and the packed a,b state. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha512)) | |
| constexpr simd< std::uint64_t, 2, Arch > | native::sha512su0 (simd< std::uint64_t, 2, Arch > w0_1, simd< std::uint64_t, 2, Arch > w2_) noexcept |
| Compute the first part of a two-word SHA-512 schedule update. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha512)) | |
| constexpr simd< std::uint64_t, 2, Arch > | native::sha512su1 (simd< std::uint64_t, 2, Arch > partial, simd< std::uint64_t, 2, Arch > w14_15, simd< std::uint64_t, 2, Arch > w9_10) noexcept |
| Finish the two-word SHA-512 schedule update from sha512su0. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3)) | |
| constexpr simd< std::uint8_t, 16, Arch > | native::eor3 (simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b, simd< std::uint8_t, 16, Arch > c) noexcept |
| Return a XOR b XOR c for every bit. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3)) | |
| constexpr simd< std::uint16_t, 8, Arch > | native::eor3 (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > c) noexcept |
| Return a XOR b XOR c for every bit. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::eor3 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept |
| Return a XOR b XOR c for every bit. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3)) | |
| constexpr simd< std::uint64_t, 2, Arch > | native::eor3 (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > c) noexcept |
| Return a XOR b XOR c for every bit. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3)) | |
| constexpr simd< std::int8_t, 16, Arch > | native::eor3 (simd< std::int8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b, simd< std::int8_t, 16, Arch > c) noexcept |
| Return a XOR b XOR c for every bit. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3)) | |
| constexpr simd< std::int16_t, 8, Arch > | native::eor3 (simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b, simd< std::int16_t, 8, Arch > c) noexcept |
| Return a XOR b XOR c for every bit. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3)) | |
| constexpr simd< std::int32_t, 4, Arch > | native::eor3 (simd< std::int32_t, 4, Arch > a, simd< std::int32_t, 4, Arch > b, simd< std::int32_t, 4, Arch > c) noexcept |
| Return a XOR b XOR c for every bit. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3)) | |
| constexpr simd< std::int64_t, 2, Arch > | native::eor3 (simd< std::int64_t, 2, Arch > a, simd< std::int64_t, 2, Arch > b, simd< std::int64_t, 2, Arch > c) noexcept |
| Return a XOR b XOR c for every bit. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3)) | |
| constexpr simd< std::uint8_t, 16, Arch > | native::bcax (simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b, simd< std::uint8_t, 16, Arch > c) noexcept |
| Return a XOR (b AND NOT c) for every bit. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3)) | |
| constexpr simd< std::uint16_t, 8, Arch > | native::bcax (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > c) noexcept |
| Return a XOR (b AND NOT c) for every bit. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::bcax (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept |
| Return a XOR (b AND NOT c) for every bit. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3)) | |
| constexpr simd< std::uint64_t, 2, Arch > | native::bcax (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > c) noexcept |
| Return a XOR (b AND NOT c) for every bit. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3)) | |
| constexpr simd< std::int8_t, 16, Arch > | native::bcax (simd< std::int8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b, simd< std::int8_t, 16, Arch > c) noexcept |
| Return a XOR (b AND NOT c) for every bit. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3)) | |
| constexpr simd< std::int16_t, 8, Arch > | native::bcax (simd< std::int16_t, 8, Arch > a, simd< std::int16_t, 8, Arch > b, simd< std::int16_t, 8, Arch > c) noexcept |
| Return a XOR (b AND NOT c) for every bit. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3)) | |
| constexpr simd< std::int32_t, 4, Arch > | native::bcax (simd< std::int32_t, 4, Arch > a, simd< std::int32_t, 4, Arch > b, simd< std::int32_t, 4, Arch > c) noexcept |
| Return a XOR (b AND NOT c) for every bit. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3)) | |
| constexpr simd< std::int64_t, 2, Arch > | native::bcax (simd< std::int64_t, 2, Arch > a, simd< std::int64_t, 2, Arch > b, simd< std::int64_t, 2, Arch > c) noexcept |
| Return a XOR (b AND NOT c) for every bit. | |
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template<isa< arm > Arch> requires (Arch.has(arm_feature::sha3)) | |
| constexpr simd< std::uint64_t, 2, Arch > | native::rax1 (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept |
| Return a XOR rotate_left(b, 1) in each 64-bit lane. | |
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template<isa< arm > Arch, unsigned Rotate> requires (Arch.has(arm_feature::sha3) && Rotate < 64) | |
| constexpr simd< std::uint64_t, 2, Arch > | native::xar (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept |
| Rotate a XOR b right by Rotate bits in each 64-bit lane; Rotate is in [0, 63]. | |
| template<isa< arm > Arch, class... T> | |
| void | native::sha1c (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
| template<isa< arm > Arch, class... T> | |
| void | native::sha1p (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
| template<isa< arm > Arch, class... T> | |
| void | native::sha1m (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
| template<isa< arm > Arch = NATIVE_BASELINE, class... T> | |
| void | native::sha1h (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
| template<isa< arm > Arch, class... T> | |
| void | native::sha1su0 (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
| template<isa< arm > Arch, class... T> | |
| void | native::sha1su1 (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
| template<isa< arm > Arch, class... T> | |
| void | native::sha256h (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
| template<isa< arm > Arch, class... T> | |
| void | native::sha256h2 (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
| template<isa< arm > Arch, class... T> | |
| void | native::sha256su0 (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
| template<isa< arm > Arch, class... T> | |
| void | native::sha256su1 (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
| template<isa< arm > Arch, class... T> | |
| void | native::sha512h (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
| template<isa< arm > Arch, class... T> | |
| void | native::sha512h2 (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
| template<isa< arm > Arch, class... T> | |
| void | native::sha512su0 (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
| template<isa< arm > Arch, class... T> | |
| void | native::sha512su1 (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
| template<isa< arm > Arch, class... T> | |
| void | native::eor3 (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
| template<isa< arm > Arch, class... T> | |
| void | native::bcax (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
| template<isa< arm > Arch, class... T> | |
| void | native::rax1 (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
| template<isa< arm > Arch, unsigned Rotate, class... T> | |
| void | native::xar (T...)=delete |
| Reject unsupported argument shapes or unavailable instruction features. | |
SHA-1, SHA-256 and SHA-512 state/schedule operations and SHA-3 Boolean helpers. These are individual instructions, not complete hash functions. Lane zero contains the first named word. Inputs contain native integer words: callers perform message byte-order conversion and supply constants. Arch names the instruction feature. SHA-1/SHA-256 use compiler "sha2"; SHA-512/SHA-3 use "sha3". Admit that complete target_features set before entering the target leaf; compiler bundles include sibling features. These integer operations do not read or modify FPCR, FPSR or NZCV. Constant evaluation computes the same integer values. Feature-absent calls are immediate-only and still require complete SIMD storage for their Arch.
1.18.0