AVX-512CD

Collaboration diagram for AVX-512CD:

Functions
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	native::vpconflictd (simd< std::uint32_t, 4, Arch > value) noexcept
	For each 32-bit lane, set bit j when earlier source lane j is equal.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	native::mask_vpconflictd (simd< std::uint32_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > value) noexcept
	Inactive destination lanes retain source; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	native::maskz_vpconflictd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > value) noexcept
	Inactive destination lanes become zero; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	native::vplzcntd (simd< std::uint32_t, 4, Arch > value) noexcept
	Count leading zeros in each 32-bit lane; zero yields 32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	native::mask_vplzcntd (simd< std::uint32_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > value) noexcept
	Inactive destination lanes retain source; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	native::maskz_vplzcntd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > value) noexcept
	Inactive destination lanes become zero; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	native::vpconflictq (simd< std::uint64_t, 2, Arch > value) noexcept
	For each 64-bit lane, set bit j when earlier source lane j is equal.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	native::mask_vpconflictq (simd< std::uint64_t, 2, Arch > source, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > value) noexcept
	Inactive destination lanes retain source; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	native::maskz_vpconflictq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > value) noexcept
	Inactive destination lanes become zero; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	native::vplzcntq (simd< std::uint64_t, 2, Arch > value) noexcept
	Count leading zeros in each 64-bit lane; zero yields 64.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	native::mask_vplzcntq (simd< std::uint64_t, 2, Arch > source, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > value) noexcept
	Inactive destination lanes retain source; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	native::maskz_vplzcntq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > value) noexcept
	Inactive destination lanes become zero; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	native::vpconflictd (simd< std::uint32_t, 8, Arch > value) noexcept
	For each 32-bit lane, set bit j when earlier source lane j is equal.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	native::mask_vpconflictd (simd< std::uint32_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > value) noexcept
	Inactive destination lanes retain source; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	native::maskz_vpconflictd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > value) noexcept
	Inactive destination lanes become zero; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	native::vplzcntd (simd< std::uint32_t, 8, Arch > value) noexcept
	Count leading zeros in each 32-bit lane; zero yields 32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	native::mask_vplzcntd (simd< std::uint32_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > value) noexcept
	Inactive destination lanes retain source; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	native::maskz_vplzcntd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > value) noexcept
	Inactive destination lanes become zero; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	native::vpconflictq (simd< std::uint64_t, 4, Arch > value) noexcept
	For each 64-bit lane, set bit j when earlier source lane j is equal.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	native::mask_vpconflictq (simd< std::uint64_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > value) noexcept
	Inactive destination lanes retain source; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	native::maskz_vpconflictq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > value) noexcept
	Inactive destination lanes become zero; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	native::vplzcntq (simd< std::uint64_t, 4, Arch > value) noexcept
	Count leading zeros in each 64-bit lane; zero yields 64.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	native::mask_vplzcntq (simd< std::uint64_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > value) noexcept
	Inactive destination lanes retain source; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	native::maskz_vplzcntq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > value) noexcept
	Inactive destination lanes become zero; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint32_t, 16, Arch >	native::vpconflictd (simd< std::uint32_t, 16, Arch > value) noexcept
	For each 32-bit lane, set bit j when earlier source lane j is equal.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint32_t, 16, Arch >	native::mask_vpconflictd (simd< std::uint32_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > value) noexcept
	Inactive destination lanes retain source; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint32_t, 16, Arch >	native::maskz_vpconflictd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > value) noexcept
	Inactive destination lanes become zero; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint32_t, 16, Arch >	native::vplzcntd (simd< std::uint32_t, 16, Arch > value) noexcept
	Count leading zeros in each 32-bit lane; zero yields 32.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint32_t, 16, Arch >	native::mask_vplzcntd (simd< std::uint32_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > value) noexcept
	Inactive destination lanes retain source; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint32_t, 16, Arch >	native::maskz_vplzcntd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > value) noexcept
	Inactive destination lanes become zero; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint64_t, 8, Arch >	native::vpconflictq (simd< std::uint64_t, 8, Arch > value) noexcept
	For each 64-bit lane, set bit j when earlier source lane j is equal.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint64_t, 8, Arch >	native::mask_vpconflictq (simd< std::uint64_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > value) noexcept
	Inactive destination lanes retain source; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint64_t, 8, Arch >	native::maskz_vpconflictq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > value) noexcept
	Inactive destination lanes become zero; every input lane still participates.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint64_t, 8, Arch >	native::vplzcntq (simd< std::uint64_t, 8, Arch > value) noexcept
	Count leading zeros in each 64-bit lane; zero yields 64.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint64_t, 8, Arch >	native::mask_vplzcntq (simd< std::uint64_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > value) noexcept
	Inactive destination lanes retain source; zero input yields the lane width.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512cd))
constexpr simd< std::uint64_t, 8, Arch >	native::maskz_vplzcntq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > value) noexcept
	Inactive destination lanes become zero; zero input yields the lane width.
template<isa< x86 > Arch, class... Args>
void	native::vpconflictd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::mask_vpconflictd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::maskz_vpconflictd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::vplzcntd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::mask_vplzcntd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::maskz_vplzcntd (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::vpconflictq (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::mask_vpconflictq (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::maskz_vpconflictq (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::vplzcntq (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::mask_vplzcntq (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::maskz_vplzcntq (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.

Detailed Description

Conflict detection and leading-zero counts for 32-bit and 64-bit lanes. Runtime calls require AVX512F and AVX512CD; 128/256-bit forms also require AVX512VL. Admit CPU features and OS ZMM state before a matching target scope. Conflict bits refer to every earlier source lane, including masked-off lanes. Masks affect destination lanes only. Zero inputs have 32/64 leading zeros. Constant evaluation uses exact integer semantics. Tags without instruction features are compile-time-only and require complete SIMD storage.