AVX-512BITALG

Collaboration diagram for AVX-512BITALG:

Functions
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	native::vpopcntb (simd< std::uint8_t, 16, Arch > value) noexcept
	Count set bits in each 8-bit lane.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	native::mask_vpopcntb (simd< std::uint8_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Inactive destination lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	native::maskz_vpopcntb (predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Inactive destination lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	native::vpopcntw (simd< std::uint16_t, 8, Arch > value) noexcept
	Count set bits in each 16-bit lane.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	native::mask_vpopcntw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Inactive destination lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	native::maskz_vpopcntw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Inactive destination lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr predicate< 16, Arch >	native::vpshufbitqmb (simd< std::uint64_t, 2, Arch > value, simd< std::uint8_t, 16, Arch > control) noexcept
	Select one source bit for each control byte, within the corresponding qword.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr predicate< 16, Arch >	native::mask_vpshufbitqmb (predicate< 16, Arch > maskmask, simd< std::uint64_t, 2, Arch > value, simd< std::uint8_t, 16, Arch > control) noexcept
	Select source bits for active output positions; inactive predicate bits become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	native::vpopcntb (simd< std::uint8_t, 32, Arch > value) noexcept
	Count set bits in each 8-bit lane.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	native::mask_vpopcntb (simd< std::uint8_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Inactive destination lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	native::maskz_vpopcntb (predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Inactive destination lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	native::vpopcntw (simd< std::uint16_t, 16, Arch > value) noexcept
	Count set bits in each 16-bit lane.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	native::mask_vpopcntw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Inactive destination lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	native::maskz_vpopcntw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Inactive destination lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr predicate< 32, Arch >	native::vpshufbitqmb (simd< std::uint64_t, 4, Arch > value, simd< std::uint8_t, 32, Arch > control) noexcept
	Select one source bit for each control byte, within the corresponding qword.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg) && Arch.has(x86_feature::avx512vl))
constexpr predicate< 32, Arch >	native::mask_vpshufbitqmb (predicate< 32, Arch > maskmask, simd< std::uint64_t, 4, Arch > value, simd< std::uint8_t, 32, Arch > control) noexcept
	Select source bits for active output positions; inactive predicate bits become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg))
constexpr simd< std::uint8_t, 64, Arch >	native::vpopcntb (simd< std::uint8_t, 64, Arch > value) noexcept
	Count set bits in each 8-bit lane.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg))
constexpr simd< std::uint8_t, 64, Arch >	native::mask_vpopcntb (simd< std::uint8_t, 64, Arch > source, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Inactive destination lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg))
constexpr simd< std::uint8_t, 64, Arch >	native::maskz_vpopcntb (predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Inactive destination lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg))
constexpr simd< std::uint16_t, 32, Arch >	native::vpopcntw (simd< std::uint16_t, 32, Arch > value) noexcept
	Count set bits in each 16-bit lane.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg))
constexpr simd< std::uint16_t, 32, Arch >	native::mask_vpopcntw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Inactive destination lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg))
constexpr simd< std::uint16_t, 32, Arch >	native::maskz_vpopcntw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Inactive destination lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg))
constexpr predicate< 64, Arch >	native::vpshufbitqmb (simd< std::uint64_t, 8, Arch > value, simd< std::uint8_t, 64, Arch > control) noexcept
	Select one source bit for each control byte, within the corresponding qword.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512bitalg))
constexpr predicate< 64, Arch >	native::mask_vpshufbitqmb (predicate< 64, Arch > maskmask, simd< std::uint64_t, 8, Arch > value, simd< std::uint8_t, 64, Arch > control) noexcept
	Select source bits for active output positions; inactive predicate bits become zero.
template<isa< x86 > Arch, class... Args>
void	native::vpopcntb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::mask_vpopcntb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::maskz_vpopcntb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::vpopcntw (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::mask_vpopcntw (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::maskz_vpopcntw (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::vpshufbitqmb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.
template<isa< x86 > Arch, class... Args>
void	native::mask_vpshufbitqmb (Args...)=delete
	Reject unsupported signatures, including implicit raw-register conversions.

Detailed Description

Byte/word population counts and qword bit selection into compact predicates. Runtime targets require AVX512F, AVX512BW and AVX512BITALG; 128/256-bit forms also require AVX512VL. AVX512BW follows Clang's BITALG target closure. Admit CPU features and OS ZMM state before entering a matching target scope. Population masks merge or zero destination lanes. Bitshuffle masks zero inactive result bits. Control bytes select bits 0..63 of their source qword. Constant evaluation uses exact integer semantics. Tags without instruction features are compile-time-only and require complete SIMD storage.