AVX-IFMA / AVX-512IFMA

Collaboration diagram for AVX-IFMA / AVX-512IFMA:

Functions
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxifma) && Arch.has(x86_feature::avx))
constexpr simd< std::uint64_t, 2, Arch >	native::madd52lo (simd< std::uint64_t, 2, Arch > accumulator, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Accumulate low 52-bit products in 2 lanes; unmasked.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxifma) && Arch.has(x86_feature::avx))
constexpr simd< std::uint64_t, 4, Arch >	native::madd52lo (simd< std::uint64_t, 4, Arch > accumulator, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Accumulate low 52-bit products in 4 lanes; unmasked.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma))
constexpr simd< std::uint64_t, 8, Arch >	native::madd52lo (simd< std::uint64_t, 8, Arch > accumulator, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Accumulate low 52-bit products in 8 lanes; unmasked.
template<isa< x86 > Arch, class... Args>
void	native::madd52lo (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector or mask shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	native::mask_madd52lo (simd< std::uint64_t, 2, Arch > accumulator, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Accumulate low 52-bit products in 2 lanes; inactive lanes retain the accumulator.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	native::mask_madd52lo (simd< std::uint64_t, 4, Arch > accumulator, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Accumulate low 52-bit products in 4 lanes; inactive lanes retain the accumulator.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma))
constexpr simd< std::uint64_t, 8, Arch >	native::mask_madd52lo (simd< std::uint64_t, 8, Arch > accumulator, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Accumulate low 52-bit products in 8 lanes; inactive lanes retain the accumulator.
template<isa< x86 > Arch, class... Args>
void	native::mask_madd52lo (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector or mask shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	native::maskz_madd52lo (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > accumulator, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Accumulate low 52-bit products in 2 lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	native::maskz_madd52lo (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > accumulator, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Accumulate low 52-bit products in 4 lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma))
constexpr simd< std::uint64_t, 8, Arch >	native::maskz_madd52lo (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > accumulator, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Accumulate low 52-bit products in 8 lanes; inactive lanes become zero.
template<isa< x86 > Arch, class... Args>
void	native::maskz_madd52lo (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector or mask shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxifma) && Arch.has(x86_feature::avx))
constexpr simd< std::uint64_t, 2, Arch >	native::madd52hi (simd< std::uint64_t, 2, Arch > accumulator, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Accumulate high 52-bit products in 2 lanes; unmasked.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avxifma) && Arch.has(x86_feature::avx))
constexpr simd< std::uint64_t, 4, Arch >	native::madd52hi (simd< std::uint64_t, 4, Arch > accumulator, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Accumulate high 52-bit products in 4 lanes; unmasked.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma))
constexpr simd< std::uint64_t, 8, Arch >	native::madd52hi (simd< std::uint64_t, 8, Arch > accumulator, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Accumulate high 52-bit products in 8 lanes; unmasked.
template<isa< x86 > Arch, class... Args>
void	native::madd52hi (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector or mask shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	native::mask_madd52hi (simd< std::uint64_t, 2, Arch > accumulator, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Accumulate high 52-bit products in 2 lanes; inactive lanes retain the accumulator.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	native::mask_madd52hi (simd< std::uint64_t, 4, Arch > accumulator, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Accumulate high 52-bit products in 4 lanes; inactive lanes retain the accumulator.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma))
constexpr simd< std::uint64_t, 8, Arch >	native::mask_madd52hi (simd< std::uint64_t, 8, Arch > accumulator, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Accumulate high 52-bit products in 8 lanes; inactive lanes retain the accumulator.
template<isa< x86 > Arch, class... Args>
void	native::mask_madd52hi (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector or mask shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	native::maskz_madd52hi (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > accumulator, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Accumulate high 52-bit products in 2 lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	native::maskz_madd52hi (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > accumulator, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Accumulate high 52-bit products in 4 lanes; inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512ifma))
constexpr simd< std::uint64_t, 8, Arch >	native::maskz_madd52hi (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > accumulator, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Accumulate high 52-bit products in 8 lanes; inactive lanes become zero.
template<isa< x86 > Arch, class... Args>
void	native::maskz_madd52hi (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector or mask shapes.

Detailed Description

Multiply the low 52 bits of each input lane and add either product half to the full 64-bit accumulator, modulo 2^64. Short unmasked operations use AVX-IFMA when tagged; otherwise they require AVX512IFMA and AVX512VL. Masked forms require EVEX; inactive lanes retain the accumulator or zero. Missing-feature overloads are consteval-only and require complete storage.