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native 0.0.1
Vectors, masks and wide register packs for C++26
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Functions | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::sm3) && Arch.has(x86_feature::avx)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sm3msg1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept |
| First SM3 schedule step. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::sm3) && Arch.has(x86_feature::avx)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sm3msg2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept |
| Final SM3 schedule step. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::sm3) && Arch.has(x86_feature::avx) && Imm8 <= 255) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sm3rnds2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept |
| Two SM3 rounds; Imm8 is masked with 0x3e. a holds unrotated CDGH and b holds ABEF. | |
| template<isa< x86 > Arch, class... Args> | |
| void | native::sm3msg1 (Args...)=delete |
| Reject raw registers, mixed requirements and unsupported shapes. | |
| template<isa< x86 > Arch, class... Args> | |
| void | native::sm3msg2 (Args...)=delete |
| Reject raw registers, mixed requirements and unsupported shapes. | |
| template<isa< x86 > Arch, unsigned Imm8, class... Args> | |
| void | native::sm3rnds2 (Args...)=delete |
| Reject raw registers, mixed requirements and unsupported shapes. | |
Runtime calls require AVX and SM3, matching compiler targets and OS vector state. Constant evaluation preserves the instruction lane packing and modulo-word arithmetic. Missing-feature overloads are constant-evaluation-only.