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native 0.0.1
Vectors, masks and wide register packs for C++26
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Functions | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::sm4) && Arch.has(x86_feature::avx)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sm4rnds4 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept |
| Four SM4 data rounds independently within each 128-bit block; a is state, b is keys. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::sm4) && Arch.has(x86_feature::avx)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sm4key4 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept |
| Four SM4 key-schedule rounds independently within each 128-bit block; a is state, b is constants. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::sm4) && Arch.has(x86_feature::avx)) | |
| constexpr simd< std::uint32_t, 8, Arch > | native::sm4rnds4 (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept |
| Four SM4 data rounds independently within each 128-bit block; a is state, b is keys. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::sm4) && Arch.has(x86_feature::avx)) | |
| constexpr simd< std::uint32_t, 8, Arch > | native::sm4key4 (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept |
| Four SM4 key-schedule rounds independently within each 128-bit block; a is state, b is constants. | |
| template<isa< x86 > Arch, class... Args> | |
| void | native::sm4rnds4 (Args...)=delete |
| Reject raw registers, mixed requirements and unsupported shapes. | |
| template<isa< x86 > Arch, class... Args> | |
| void | native::sm4key4 (Args...)=delete |
| Reject raw registers, mixed requirements and unsupported shapes. | |
Runtime calls require AVX and SM4, matching compiler targets and OS vector state. Constant evaluation preserves the instruction lane packing and modulo-word arithmetic. Missing-feature overloads are constant-evaluation-only.