VAES

Collaboration diagram for VAES:

Functions
template<isa< x86 > Arch> requires (Arch.has(x86_feature::aes) && Arch.has(x86_feature::avx))
constexpr simd< std::uint8_t, 16, Arch >	native::vaesenc (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > key) noexcept
	One AES encryption round.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx))
constexpr simd< std::uint8_t, 32, Arch >	native::vaesenc (simd< std::uint8_t, 32, Arch > state, simd< std::uint8_t, 32, Arch > key) noexcept
	Two independent AES encryption rounds.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx512f))
constexpr simd< std::uint8_t, 64, Arch >	native::vaesenc (simd< std::uint8_t, 64, Arch > state, simd< std::uint8_t, 64, Arch > key) noexcept
	Four independent AES encryption rounds.
template<isa< x86 > Arch, class... Args>
void	native::vaesenc (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::aes) && Arch.has(x86_feature::avx))
constexpr simd< std::uint8_t, 16, Arch >	native::vaesenclast (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > key) noexcept
	One final AES encryption round.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx))
constexpr simd< std::uint8_t, 32, Arch >	native::vaesenclast (simd< std::uint8_t, 32, Arch > state, simd< std::uint8_t, 32, Arch > key) noexcept
	Two independent final AES encryption rounds.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx512f))
constexpr simd< std::uint8_t, 64, Arch >	native::vaesenclast (simd< std::uint8_t, 64, Arch > state, simd< std::uint8_t, 64, Arch > key) noexcept
	Four independent final AES encryption rounds.
template<isa< x86 > Arch, class... Args>
void	native::vaesenclast (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::aes) && Arch.has(x86_feature::avx))
constexpr simd< std::uint8_t, 16, Arch >	native::vaesdec (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > key) noexcept
	One AES decryption round.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx))
constexpr simd< std::uint8_t, 32, Arch >	native::vaesdec (simd< std::uint8_t, 32, Arch > state, simd< std::uint8_t, 32, Arch > key) noexcept
	Two independent AES decryption rounds.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx512f))
constexpr simd< std::uint8_t, 64, Arch >	native::vaesdec (simd< std::uint8_t, 64, Arch > state, simd< std::uint8_t, 64, Arch > key) noexcept
	Four independent AES decryption rounds.
template<isa< x86 > Arch, class... Args>
void	native::vaesdec (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector shapes.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::aes) && Arch.has(x86_feature::avx))
constexpr simd< std::uint8_t, 16, Arch >	native::vaesdeclast (simd< std::uint8_t, 16, Arch > state, simd< std::uint8_t, 16, Arch > key) noexcept
	One final AES decryption round.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx))
constexpr simd< std::uint8_t, 32, Arch >	native::vaesdeclast (simd< std::uint8_t, 32, Arch > state, simd< std::uint8_t, 32, Arch > key) noexcept
	Two independent final AES decryption rounds.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::vaes) && Arch.has(x86_feature::avx512f))
constexpr simd< std::uint8_t, 64, Arch >	native::vaesdeclast (simd< std::uint8_t, 64, Arch > state, simd< std::uint8_t, 64, Arch > key) noexcept
	Four independent final AES decryption rounds.
template<isa< x86 > Arch, class... Args>
void	native::vaesdeclast (Args...)=delete
	Reject raw registers, mixed tags and unsupported vector shapes.

Detailed Description

Independent 128-bit AES states in register order. The 128-bit VEX forms require AES and AVX; the 256-bit forms require VAES and AVX; the 512-bit forms require VAES and AVX512F. There are no instruction writemasks. Arch records requirements; callers separately enable and admit the target. Constant evaluation computes exact AES results. Missing-feature forms are consteval-only and require complete SIMD storage for the selected width.