AVX-512VBMI2

Collaboration diagram for AVX-512VBMI2:

Functions
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	native::mask_vpcompressb (simd< std::uint8_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	native::maskz_vpcompressb (predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Remaining result lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr void	native::mask_vpcompressb (std::uint8_t *destination, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Store selected lanes in order; destination has popcount(mask) writable elements, or may be null if empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	native::mask_vpexpandb (simd< std::uint8_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 16, Arch >	native::maskz_vpexpandb (predicate< 16, Arch > maskmask, simd< std::uint8_t, 16, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Remaining result lanes become zero.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && (std::same_as<T, std::uint8_t> || std::same_as<T, std::uint8_t const>))
constexpr simd< std::uint8_t, 16, Arch >	native::mask_vpexpandb (simd< std::uint8_t, 16, Arch > source, predicate< 16, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && (std::same_as<T, std::uint8_t> || std::same_as<T, std::uint8_t const>))
constexpr simd< std::uint8_t, 16, Arch >	native::maskz_vpexpandb (predicate< 16, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	native::mask_vpcompressw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	native::maskz_vpcompressw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Remaining result lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr void	native::mask_vpcompressw (std::uint16_t *destination, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Store selected lanes in order; destination has popcount(mask) writable elements, or may be null if empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	native::mask_vpexpandw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	native::maskz_vpexpandw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Remaining result lanes become zero.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && (std::same_as<T, std::uint16_t> || std::same_as<T, std::uint16_t const>))
constexpr simd< std::uint16_t, 8, Arch >	native::mask_vpexpandw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && (std::same_as<T, std::uint16_t> || std::same_as<T, std::uint16_t const>))
constexpr simd< std::uint16_t, 8, Arch >	native::maskz_vpexpandw (predicate< 8, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 8, Arch >	native::vpshldw (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 8, Arch >	native::mask_vpshldw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 8, Arch >	native::maskz_vpshldw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	native::vpshldvw (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	native::mask_vpshldvw (simd< std::uint16_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	native::maskz_vpshldvw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 8, Arch >	native::vpshrdw (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 8, Arch >	native::mask_vpshrdw (simd< std::uint16_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 8, Arch >	native::maskz_vpshrdw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	native::vpshrdvw (simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	native::mask_vpshrdvw (simd< std::uint16_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 8, Arch >	native::maskz_vpshrdvw (predicate< 8, Arch > maskmask, simd< std::uint16_t, 8, Arch > a, simd< std::uint16_t, 8, Arch > b, simd< std::uint16_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 4, Arch >	native::vpshldd (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 4, Arch >	native::mask_vpshldd (simd< std::uint32_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 4, Arch >	native::maskz_vpshldd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	native::vpshldvd (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	native::mask_vpshldvd (simd< std::uint32_t, 4, Arch > a, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	native::maskz_vpshldvd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 4, Arch >	native::vpshrdd (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 4, Arch >	native::mask_vpshrdd (simd< std::uint32_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 4, Arch >	native::maskz_vpshrdd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	native::vpshrdvd (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	native::mask_vpshrdvd (simd< std::uint32_t, 4, Arch > a, predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 4, Arch >	native::maskz_vpshrdvd (predicate< 4, Arch > maskmask, simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 2, Arch >	native::vpshldq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 2, Arch >	native::mask_vpshldq (simd< std::uint64_t, 2, Arch > source, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 2, Arch >	native::maskz_vpshldq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	native::vpshldvq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	native::mask_vpshldvq (simd< std::uint64_t, 2, Arch > a, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	native::maskz_vpshldvq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 2, Arch >	native::vpshrdq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 2, Arch >	native::mask_vpshrdq (simd< std::uint64_t, 2, Arch > source, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 2, Arch >	native::maskz_vpshrdq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	native::vpshrdvq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	native::mask_vpshrdvq (simd< std::uint64_t, 2, Arch > a, predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 2, Arch >	native::maskz_vpshrdvq (predicate< 2, Arch > maskmask, simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b, simd< std::uint64_t, 2, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	native::mask_vpcompressb (simd< std::uint8_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	native::maskz_vpcompressb (predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Remaining result lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr void	native::mask_vpcompressb (std::uint8_t *destination, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Store selected lanes in order; destination has popcount(mask) writable elements, or may be null if empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	native::mask_vpexpandb (simd< std::uint8_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint8_t, 32, Arch >	native::maskz_vpexpandb (predicate< 32, Arch > maskmask, simd< std::uint8_t, 32, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Remaining result lanes become zero.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && (std::same_as<T, std::uint8_t> || std::same_as<T, std::uint8_t const>))
constexpr simd< std::uint8_t, 32, Arch >	native::mask_vpexpandb (simd< std::uint8_t, 32, Arch > source, predicate< 32, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && (std::same_as<T, std::uint8_t> || std::same_as<T, std::uint8_t const>))
constexpr simd< std::uint8_t, 32, Arch >	native::maskz_vpexpandb (predicate< 32, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	native::mask_vpcompressw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	native::maskz_vpcompressw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Remaining result lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr void	native::mask_vpcompressw (std::uint16_t *destination, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Store selected lanes in order; destination has popcount(mask) writable elements, or may be null if empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	native::mask_vpexpandw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	native::maskz_vpexpandw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Remaining result lanes become zero.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && (std::same_as<T, std::uint16_t> || std::same_as<T, std::uint16_t const>))
constexpr simd< std::uint16_t, 16, Arch >	native::mask_vpexpandw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && (std::same_as<T, std::uint16_t> || std::same_as<T, std::uint16_t const>))
constexpr simd< std::uint16_t, 16, Arch >	native::maskz_vpexpandw (predicate< 16, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 16, Arch >	native::vpshldw (simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 16, Arch >	native::mask_vpshldw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 16, Arch >	native::maskz_vpshldw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	native::vpshldvw (simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	native::mask_vpshldvw (simd< std::uint16_t, 16, Arch > a, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	native::maskz_vpshldvw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 16, Arch >	native::vpshrdw (simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 16, Arch >	native::mask_vpshrdw (simd< std::uint16_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint16_t, 16, Arch >	native::maskz_vpshrdw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	native::vpshrdvw (simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	native::mask_vpshrdvw (simd< std::uint16_t, 16, Arch > a, predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint16_t, 16, Arch >	native::maskz_vpshrdvw (predicate< 16, Arch > maskmask, simd< std::uint16_t, 16, Arch > a, simd< std::uint16_t, 16, Arch > b, simd< std::uint16_t, 16, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 8, Arch >	native::vpshldd (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 8, Arch >	native::mask_vpshldd (simd< std::uint32_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 8, Arch >	native::maskz_vpshldd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	native::vpshldvd (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	native::mask_vpshldvd (simd< std::uint32_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	native::maskz_vpshldvd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 8, Arch >	native::vpshrdd (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 8, Arch >	native::mask_vpshrdd (simd< std::uint32_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint32_t, 8, Arch >	native::maskz_vpshrdd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	native::vpshrdvd (simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	native::mask_vpshrdvd (simd< std::uint32_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint32_t, 8, Arch >	native::maskz_vpshrdvd (predicate< 8, Arch > maskmask, simd< std::uint32_t, 8, Arch > a, simd< std::uint32_t, 8, Arch > b, simd< std::uint32_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 4, Arch >	native::vpshldq (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 4, Arch >	native::mask_vpshldq (simd< std::uint64_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 4, Arch >	native::maskz_vpshldq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	native::vpshldvq (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	native::mask_vpshldvq (simd< std::uint64_t, 4, Arch > a, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	native::maskz_vpshldvq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 4, Arch >	native::vpshrdq (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 4, Arch >	native::mask_vpshrdq (simd< std::uint64_t, 4, Arch > source, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255)
constexpr simd< std::uint64_t, 4, Arch >	native::maskz_vpshrdq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	native::vpshrdvq (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	native::mask_vpshrdvq (simd< std::uint64_t, 4, Arch > a, predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Arch.has(x86_feature::avx512vl))
constexpr simd< std::uint64_t, 4, Arch >	native::maskz_vpshrdvq (predicate< 4, Arch > maskmask, simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b, simd< std::uint64_t, 4, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint8_t, 64, Arch >	native::mask_vpcompressb (simd< std::uint8_t, 64, Arch > source, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint8_t, 64, Arch >	native::maskz_vpcompressb (predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Remaining result lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr void	native::mask_vpcompressb (std::uint8_t *destination, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Store selected lanes in order; destination has popcount(mask) writable elements, or may be null if empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint8_t, 64, Arch >	native::mask_vpexpandb (simd< std::uint8_t, 64, Arch > source, predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint8_t, 64, Arch >	native::maskz_vpexpandb (predicate< 64, Arch > maskmask, simd< std::uint8_t, 64, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Remaining result lanes become zero.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && (std::same_as<T, std::uint8_t> || std::same_as<T, std::uint8_t const>))
constexpr simd< std::uint8_t, 64, Arch >	native::mask_vpexpandb (simd< std::uint8_t, 64, Arch > source, predicate< 64, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && (std::same_as<T, std::uint8_t> || std::same_as<T, std::uint8_t const>))
constexpr simd< std::uint8_t, 64, Arch >	native::maskz_vpexpandb (predicate< 64, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	native::mask_vpcompressw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	native::maskz_vpcompressw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Pack selected lanes in order into the low result lanes. Remaining result lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr void	native::mask_vpcompressw (std::uint16_t *destination, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Store selected lanes in order; destination has popcount(mask) writable elements, or may be null if empty.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	native::mask_vpexpandw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Inactive result lanes retain source.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	native::maskz_vpexpandw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > value) noexcept
	Expand the packed prefix into selected lanes. Remaining result lanes become zero.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && (std::same_as<T, std::uint16_t> || std::same_as<T, std::uint16_t const>))
constexpr simd< std::uint16_t, 32, Arch >	native::mask_vpexpandw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, class T> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && (std::same_as<T, std::uint16_t> || std::same_as<T, std::uint16_t const>))
constexpr simd< std::uint16_t, 32, Arch >	native::maskz_vpexpandw (predicate< 32, Arch > maskmask, T *memory) noexcept
	Expand popcount(mask) readable elements; memory may be null if the logical mask is empty.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint16_t, 32, Arch >	native::vpshldw (simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint16_t, 32, Arch >	native::mask_vpshldw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint16_t, 32, Arch >	native::maskz_vpshldw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	native::vpshldvw (simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	native::mask_vpshldvw (simd< std::uint16_t, 32, Arch > a, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	native::maskz_vpshldvw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint16_t, 32, Arch >	native::vpshrdw (simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint16_t, 32, Arch >	native::mask_vpshrdw (simd< std::uint16_t, 32, Arch > source, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint16_t, 32, Arch >	native::maskz_vpshrdw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	native::vpshrdvw (simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	native::mask_vpshrdvw (simd< std::uint16_t, 32, Arch > a, predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint16_t, 32, Arch >	native::maskz_vpshrdvw (predicate< 32, Arch > maskmask, simd< std::uint16_t, 32, Arch > a, simd< std::uint16_t, 32, Arch > b, simd< std::uint16_t, 32, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint32_t, 16, Arch >	native::vpshldd (simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint32_t, 16, Arch >	native::mask_vpshldd (simd< std::uint32_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint32_t, 16, Arch >	native::maskz_vpshldd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint32_t, 16, Arch >	native::vpshldvd (simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint32_t, 16, Arch >	native::mask_vpshldvd (simd< std::uint32_t, 16, Arch > a, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint32_t, 16, Arch >	native::maskz_vpshldvd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint32_t, 16, Arch >	native::vpshrdd (simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint32_t, 16, Arch >	native::mask_vpshrdd (simd< std::uint32_t, 16, Arch > source, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint32_t, 16, Arch >	native::maskz_vpshrdd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint32_t, 16, Arch >	native::vpshrdvd (simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint32_t, 16, Arch >	native::mask_vpshrdvd (simd< std::uint32_t, 16, Arch > a, predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint32_t, 16, Arch >	native::maskz_vpshrdvd (predicate< 16, Arch > maskmask, simd< std::uint32_t, 16, Arch > a, simd< std::uint32_t, 16, Arch > b, simd< std::uint32_t, 16, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint64_t, 8, Arch >	native::vpshldq (simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint64_t, 8, Arch >	native::mask_vpshldq (simd< std::uint64_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint64_t, 8, Arch >	native::maskz_vpshldq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Shift concatenated lanes left using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint64_t, 8, Arch >	native::vpshldvq (simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint64_t, 8, Arch >	native::mask_vpshldvq (simd< std::uint64_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint64_t, 8, Arch >	native::maskz_vpshldvq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Shift concatenated lanes left using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint64_t, 8, Arch >	native::vpshrdq (simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint64_t, 8, Arch >	native::mask_vpshrdq (simd< std::uint64_t, 8, Arch > source, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes retain source.
template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2) && Imm8 <= 255)
constexpr simd< std::uint64_t, 8, Arch >	native::maskz_vpshrdq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept
	Shift concatenated lanes right using Imm8. Inactive lanes become zero.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint64_t, 8, Arch >	native::vpshrdvq (simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint64_t, 8, Arch >	native::mask_vpshrdvq (simd< std::uint64_t, 8, Arch > a, predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes retain a.
template<isa< x86 > Arch> requires (Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vbmi2))
constexpr simd< std::uint64_t, 8, Arch >	native::maskz_vpshrdvq (predicate< 8, Arch > maskmask, simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b, simd< std::uint64_t, 8, Arch > counts) noexcept
	Shift concatenated lanes right using per-lane counts. Inactive lanes become zero.
template<isa< x86 > Arch, class... Args>
void	native::mask_vpcompressb (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::maskz_vpcompressb (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::mask_vpexpandb (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::maskz_vpexpandb (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::mask_vpcompressw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::maskz_vpcompressw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::mask_vpexpandw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::maskz_vpexpandw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::vpshldw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::mask_vpshldw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::maskz_vpshldw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::vpshldvw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::mask_vpshldvw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::maskz_vpshldvw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::vpshrdw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::mask_vpshrdw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::maskz_vpshrdw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::vpshrdvw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::mask_vpshrdvw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::maskz_vpshrdvw (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::vpshldd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::mask_vpshldd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::maskz_vpshldd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::vpshldvd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::mask_vpshldvd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::maskz_vpshldvd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::vpshrdd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::mask_vpshrdd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::maskz_vpshrdd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::vpshrdvd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::mask_vpshrdvd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::maskz_vpshrdvd (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::vpshldq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::mask_vpshldq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::maskz_vpshldq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::vpshldvq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::mask_vpshldvq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::maskz_vpshldvq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::vpshrdq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::mask_vpshrdq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, unsigned Imm8, class... Args>
void	native::maskz_vpshrdq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::vpshrdvq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::mask_vpshrdvq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.
template<isa< x86 > Arch, class... Args>
void	native::maskz_vpshrdvq (Args...)=delete
	Reject unsupported shapes, element types, masks and pointer arguments.

Detailed Description

Byte/word compaction, packed memory transfers and double-source shifts. Runtime targets require AVX512F, AVX512BW and AVX512VBMI2; 128/256-bit forms also require AVX512VL. Admit CPU features and OS ZMM state first. Compress preserves source above the packed prefix; expand preserves source at inactive mask positions. Memory forms access exactly popcount(mask) typed elements; a null pointer is valid only for an empty logical mask. Shift counts use the low log2(element bits) bits. Immediate values must fit an unsigned byte. Variable merging forms retain a at inactive positions. Weaker feature tags support constant evaluation when storage is available.