native 0.0.1
Vectors, masks and wide register packs for C++26
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i8mm.h
1// SPDX-License-Identifier: BSD-2-Clause OR Apache-2.0
2#pragma once
4#include "native/config.h"
5#include "native/attributes.h"
6#include "native/isa.h"
7#if NATIVE_HOST_NEON
8#include <arm_neon.h>
9#endif
10#if NATIVE_HOST_NEON || defined(NATIVE_DOXYGEN)
11
12namespace native::detail {
13
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20
21 template<isa<arm> Arch> requires(Arch.has(arm_feature::i8mm))
22 native_nodiscard native_inline native_const __attribute__((target("i8mm")))
23 int32x4_t smmla(int32x4_t acc, int8x16_t a, int8x16_t b) noexcept {
24 return vmmlaq_s32(acc,a,b);
25 }
26
27 template<isa<arm> Arch> requires(Arch.has(arm_feature::i8mm))
28 native_nodiscard native_inline native_const __attribute__((target("i8mm")))
29 uint32x4_t ummla(uint32x4_t acc, uint8x16_t a, uint8x16_t b) noexcept {
30 return vmmlaq_u32(acc,a,b);
31 }
32
33 template<isa<arm> Arch> requires(Arch.has(arm_feature::i8mm))
34 native_nodiscard native_inline native_const __attribute__((target("i8mm")))
35 int32x4_t usmmla(int32x4_t acc, uint8x16_t a, int8x16_t b) noexcept {
36 return vusmmlaq_s32(acc,a,b);
37 }
38
39 template<isa<arm> Arch> requires(Arch.has(arm_feature::i8mm))
40 native_nodiscard native_inline native_const __attribute__((target("i8mm")))
41 int32x2_t usdot(int32x2_t acc, uint8x8_t a, int8x8_t b) noexcept {
42 return vusdot_s32(acc,a,b);
43 }
44
45 template<isa<arm> Arch, unsigned Lane> requires(Arch.has(arm_feature::i8mm) && Lane < 2)
46 native_nodiscard native_inline native_const __attribute__((target("i8mm")))
47 int32x2_t usdot_lane(int32x2_t acc, uint8x8_t a, int8x8_t b) noexcept {
48 return vusdot_lane_s32(acc,a,b,Lane);
49 }
50
51 template<isa<arm> Arch, unsigned Lane> requires(Arch.has(arm_feature::i8mm) && Lane < 2)
52 native_nodiscard native_inline native_const __attribute__((target("i8mm")))
53 int32x2_t sudot_lane(int32x2_t acc, int8x8_t a, uint8x8_t b) noexcept {
54 return vsudot_lane_s32(acc,a,b,Lane);
55 }
56
57 template<isa<arm> Arch, unsigned Lane> requires(Arch.has(arm_feature::i8mm) && Lane < 4)
58 native_nodiscard native_inline native_const __attribute__((target("i8mm")))
59 int32x2_t usdot_lane(int32x2_t acc, uint8x8_t a, int8x16_t b) noexcept {
60 return vusdot_laneq_s32(acc,a,b,Lane);
61 }
62
63 template<isa<arm> Arch, unsigned Lane> requires(Arch.has(arm_feature::i8mm) && Lane < 4)
64 native_nodiscard native_inline native_const __attribute__((target("i8mm")))
65 int32x2_t sudot_lane(int32x2_t acc, int8x8_t a, uint8x16_t b) noexcept {
66 return vsudot_laneq_s32(acc,a,b,Lane);
67 }
68
69 template<isa<arm> Arch> requires(Arch.has(arm_feature::i8mm))
70 native_nodiscard native_inline native_const __attribute__((target("i8mm")))
71 int32x4_t usdot(int32x4_t acc, uint8x16_t a, int8x16_t b) noexcept {
72 return vusdotq_s32(acc,a,b);
73 }
74
75 template<isa<arm> Arch, unsigned Lane> requires(Arch.has(arm_feature::i8mm) && Lane < 2)
76 native_nodiscard native_inline native_const __attribute__((target("i8mm")))
77 int32x4_t usdot_lane(int32x4_t acc, uint8x16_t a, int8x8_t b) noexcept {
78 return vusdotq_lane_s32(acc,a,b,Lane);
79 }
80
81 template<isa<arm> Arch, unsigned Lane> requires(Arch.has(arm_feature::i8mm) && Lane < 2)
82 native_nodiscard native_inline native_const __attribute__((target("i8mm")))
83 int32x4_t sudot_lane(int32x4_t acc, int8x16_t a, uint8x8_t b) noexcept {
84 return vsudotq_lane_s32(acc,a,b,Lane);
85 }
86
87 template<isa<arm> Arch, unsigned Lane> requires(Arch.has(arm_feature::i8mm) && Lane < 4)
88 native_nodiscard native_inline native_const __attribute__((target("i8mm")))
89 int32x4_t usdot_lane(int32x4_t acc, uint8x16_t a, int8x16_t b) noexcept {
90 return vusdotq_laneq_s32(acc,a,b,Lane);
91 }
92
93 template<isa<arm> Arch, unsigned Lane> requires(Arch.has(arm_feature::i8mm) && Lane < 4)
94 native_nodiscard native_inline native_const __attribute__((target("i8mm")))
95 int32x4_t sudot_lane(int32x4_t acc, int8x16_t a, uint8x16_t b) noexcept {
96 return vsudotq_laneq_s32(acc,a,b,Lane);
97 }
98
99}
100#endif
Compiler attributes for host code, with shader-safe shared modifiers.
constexpr simd< std::int32_t, 2, Arch > usdot(simd< std::int32_t, 2, Arch > acc, simd< std::uint8_t, 8, Arch > a, simd< std::int8_t, 8, Arch > b) noexcept
Accumulate each corresponding group of four unsigned a bytes times signed b bytes.
constexpr simd< std::int32_t, 2, Arch > sudot_lane(simd< std::int32_t, 2, Arch > acc, simd< std::int8_t, 8, Arch > a, simd< std::uint8_t, 8, Arch > b) noexcept
Accumulate each four-byte group of a times b[4*Lane..4*Lane+3].
constexpr simd< std::int32_t, 4, Arch > usmmla(simd< std::int32_t, 4, Arch > acc, simd< std::uint8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
Unsigned left matrix times signed right matrix, with signed accumulator.
constexpr simd< std::uint32_t, 4, Arch > ummla(simd< std::uint32_t, 4, Arch > acc, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept
Unsigned 2x8 times 8x2 matrix multiply-accumulate.
constexpr simd< std::int32_t, 4, Arch > smmla(simd< std::int32_t, 4, Arch > acc, simd< std::int8_t, 16, Arch > a, simd< std::int8_t, 16, Arch > b) noexcept
Signed 2x8 times 8x2 matrix multiply-accumulate.
constexpr simd< std::int32_t, 2, Arch > usdot_lane(simd< std::int32_t, 2, Arch > acc, simd< std::uint8_t, 8, Arch > a, simd< std::int8_t, 8, Arch > b) noexcept
Accumulate each four-byte group of a times b[4*Lane..4*Lane+3].
#define native_inline
inline [[always_inline]]
Definition attributes.h:212
#define native_nodiscard
C++17 [[nodiscard]].
Definition attributes.h:189
#define native_const
[[const]] is not const
Definition attributes.h:108
constexpr int target
First matching requirement, with every later choice checked for shadowing.
Definition isa.h:396