native.arm.bf16 Module Reference

Exported Modules
module	native.arm.features
module	native.simd

Functions
template<isa< arm > Arch> requires (Arch.has(arm_feature::neon_bf16))
constexpr simd< float, 2, Arch >	native::bfdot (simd< float, 2, Arch > acc, simd< bf16, 4, Arch > a, simd< bf16, 4, Arch > b) noexcept
	Accumulate each adjacent pair of BF16 products into the corresponding FP32 lane.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<bf16, 4, Arch>); } && !(Arch.has(arm_feature::neon_bf16)))
consteval simd< float, 2, Arch >	native::bfdot (simd< float, 2, Arch > acc, simd< bf16, 4, Arch > a, simd< bf16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::neon_bf16) && Lane < 2)
constexpr simd< float, 2, Arch >	native::bfdot_lane (simd< float, 2, Arch > acc, simd< bf16, 4, Arch > a, simd< bf16, 4, Arch > b) noexcept
	BFDOT with the BF16 pair b[2*Lane], b[2*Lane+1] shared by all output lanes.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<bf16, 4, Arch>); } && !(Arch.has(arm_feature::neon_bf16)) && Lane < 2)
consteval simd< float, 2, Arch >	native::bfdot_lane (simd< float, 2, Arch > acc, simd< bf16, 4, Arch > a, simd< bf16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::neon_bf16) && Lane < 4)
constexpr simd< float, 2, Arch >	native::bfdot_lane (simd< float, 2, Arch > acc, simd< bf16, 4, Arch > a, simd< bf16, 8, Arch > b) noexcept
	BFDOT with the BF16 pair b[2*Lane], b[2*Lane+1] shared by all output lanes.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 2, Arch>); } && requires { sizeof(simd<bf16, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && !(Arch.has(arm_feature::neon_bf16)) && Lane < 4)
consteval simd< float, 2, Arch >	native::bfdot_lane (simd< float, 2, Arch > acc, simd< bf16, 4, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch> requires (Arch.has(arm_feature::neon_bf16))
constexpr simd< float, 4, Arch >	native::bfdot (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Accumulate each adjacent pair of BF16 products into the corresponding FP32 lane.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && !(Arch.has(arm_feature::neon_bf16)))
consteval simd< float, 4, Arch >	native::bfdot (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::neon_bf16) && Lane < 2)
constexpr simd< float, 4, Arch >	native::bfdot_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 4, Arch > b) noexcept
	BFDOT with the BF16 pair b[2*Lane], b[2*Lane+1] shared by all output lanes.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && requires { sizeof(simd<bf16, 4, Arch>); } && !(Arch.has(arm_feature::neon_bf16)) && Lane < 2)
consteval simd< float, 4, Arch >	native::bfdot_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::neon_bf16) && Lane < 4)
constexpr simd< float, 4, Arch >	native::bfdot_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	BFDOT with the BF16 pair b[2*Lane], b[2*Lane+1] shared by all output lanes.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && !(Arch.has(arm_feature::neon_bf16)) && Lane < 4)
consteval simd< float, 4, Arch >	native::bfdot_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch> requires (Arch.has(arm_feature::neon_bf16))
constexpr simd< float, 4, Arch >	native::bfmmla (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Accumulate a row-major 2x4 matrix times a column-major 4x2 matrix, two BFDOT steps per result.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && !(Arch.has(arm_feature::neon_bf16)))
consteval simd< float, 4, Arch >	native::bfmmla (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch> requires (Arch.has(arm_feature::neon_bf16))
constexpr simd< float, 4, Arch >	native::bfmlalb (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Fused multiply-add of the even BF16 lanes into the corresponding FP32 lanes.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && !(Arch.has(arm_feature::neon_bf16)))
consteval simd< float, 4, Arch >	native::bfmlalb (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::neon_bf16) && Lane < 4)
constexpr simd< float, 4, Arch >	native::bfmlalb_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 4, Arch > b) noexcept
	Fused multiply-add of the even lanes of a with b[Lane] shared by all output lanes.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && requires { sizeof(simd<bf16, 4, Arch>); } && !(Arch.has(arm_feature::neon_bf16)) && Lane < 4)
consteval simd< float, 4, Arch >	native::bfmlalb_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::neon_bf16) && Lane < 8)
constexpr simd< float, 4, Arch >	native::bfmlalb_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Fused multiply-add of the even lanes of a with b[Lane] shared by all output lanes.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && !(Arch.has(arm_feature::neon_bf16)) && Lane < 8)
consteval simd< float, 4, Arch >	native::bfmlalb_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch> requires (Arch.has(arm_feature::neon_bf16))
constexpr simd< float, 4, Arch >	native::bfmlalt (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Fused multiply-add of the odd BF16 lanes into the corresponding FP32 lanes.
template<isa< arm > Arch> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && !(Arch.has(arm_feature::neon_bf16)))
consteval simd< float, 4, Arch >	native::bfmlalt (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::neon_bf16) && Lane < 4)
constexpr simd< float, 4, Arch >	native::bfmlalt_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 4, Arch > b) noexcept
	Fused multiply-add of the odd lanes of a with b[Lane] shared by all output lanes.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && requires { sizeof(simd<bf16, 4, Arch>); } && !(Arch.has(arm_feature::neon_bf16)) && Lane < 4)
consteval simd< float, 4, Arch >	native::bfmlalt_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 4, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.
template<isa< arm > Arch, unsigned Lane> requires (Arch.has(arm_feature::neon_bf16) && Lane < 8)
constexpr simd< float, 4, Arch >	native::bfmlalt_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Fused multiply-add of the odd lanes of a with b[Lane] shared by all output lanes.
template<isa< arm > Arch, unsigned Lane> requires (requires { sizeof(simd<float, 4, Arch>); } && requires { sizeof(simd<bf16, 8, Arch>); } && !(Arch.has(arm_feature::neon_bf16)) && Lane < 8)
consteval simd< float, 4, Arch >	native::bfmlalt_lane (simd< float, 4, Arch > acc, simd< bf16, 8, Arch > a, simd< bf16, 8, Arch > b) noexcept
	Constant-evaluation-only form when the instruction feature is absent.

Files
file	src/native.arm.bf16.ccm