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native 0.0.1
Vectors, masks and wide register packs for C++26
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Exported Modules | |
| module | native.x86.features |
| module | native.simd |
Functions | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni)) | |
| constexpr simd< std::uint8_t, 16, Arch > | native::gf2p8mulb (simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept |
| Multiply corresponding bytes in GF(2^8). | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 16, Arch > | native::gf2p8affineqb (simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept |
| Apply the binary matrix in each 64-bit lane and XOR Imm8. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 16, Arch > | native::gf2p8affineinvqb (simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept |
| Invert each field byte, apply its lane's binary matrix, and XOR Imm8. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl)) | |
| constexpr simd< std::uint8_t, 16, Arch > | native::gf2p8mulb_mask (simd< std::uint8_t, 16, Arch > src, predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept |
| Merge inactive bytes from src after gf2p8mulb. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl)) | |
| constexpr simd< std::uint8_t, 16, Arch > | native::gf2p8mulb_maskz (predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept |
| Zero inactive bytes after gf2p8mulb. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 16, Arch > | native::gf2p8affineqb_mask (simd< std::uint8_t, 16, Arch > src, predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept |
| Merge inactive bytes from src after gf2p8affineqb. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 16, Arch > | native::gf2p8affineqb_maskz (predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept |
| Zero inactive bytes after gf2p8affineqb. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 16, Arch > | native::gf2p8affineinvqb_mask (simd< std::uint8_t, 16, Arch > src, predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept |
| Merge inactive bytes from src after gf2p8affineinvqb. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 16, Arch > | native::gf2p8affineinvqb_maskz (predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept |
| Zero inactive bytes after gf2p8affineinvqb. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx)) | |
| constexpr simd< std::uint8_t, 32, Arch > | native::gf2p8mulb (simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept |
| Multiply corresponding bytes in GF(2^8). | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 32, Arch > | native::gf2p8affineqb (simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept |
| Apply the binary matrix in each 64-bit lane and XOR Imm8. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 32, Arch > | native::gf2p8affineinvqb (simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept |
| Invert each field byte, apply its lane's binary matrix, and XOR Imm8. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl)) | |
| constexpr simd< std::uint8_t, 32, Arch > | native::gf2p8mulb_mask (simd< std::uint8_t, 32, Arch > src, predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept |
| Merge inactive bytes from src after gf2p8mulb. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl)) | |
| constexpr simd< std::uint8_t, 32, Arch > | native::gf2p8mulb_maskz (predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept |
| Zero inactive bytes after gf2p8mulb. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 32, Arch > | native::gf2p8affineqb_mask (simd< std::uint8_t, 32, Arch > src, predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept |
| Merge inactive bytes from src after gf2p8affineqb. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 32, Arch > | native::gf2p8affineqb_maskz (predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept |
| Zero inactive bytes after gf2p8affineqb. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 32, Arch > | native::gf2p8affineinvqb_mask (simd< std::uint8_t, 32, Arch > src, predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept |
| Merge inactive bytes from src after gf2p8affineinvqb. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 32, Arch > | native::gf2p8affineinvqb_maskz (predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept |
| Zero inactive bytes after gf2p8affineinvqb. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f)) | |
| constexpr simd< std::uint8_t, 64, Arch > | native::gf2p8mulb (simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept |
| Multiply corresponding bytes in GF(2^8). | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 64, Arch > | native::gf2p8affineqb (simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept |
| Apply the binary matrix in each 64-bit lane and XOR Imm8. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 64, Arch > | native::gf2p8affineinvqb (simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept |
| Invert each field byte, apply its lane's binary matrix, and XOR Imm8. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw)) | |
| constexpr simd< std::uint8_t, 64, Arch > | native::gf2p8mulb_mask (simd< std::uint8_t, 64, Arch > src, predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept |
| Merge inactive bytes from src after gf2p8mulb. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw)) | |
| constexpr simd< std::uint8_t, 64, Arch > | native::gf2p8mulb_maskz (predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept |
| Zero inactive bytes after gf2p8mulb. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 64, Arch > | native::gf2p8affineqb_mask (simd< std::uint8_t, 64, Arch > src, predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept |
| Merge inactive bytes from src after gf2p8affineqb. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 64, Arch > | native::gf2p8affineqb_maskz (predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept |
| Zero inactive bytes after gf2p8affineqb. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 64, Arch > | native::gf2p8affineinvqb_mask (simd< std::uint8_t, 64, Arch > src, predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept |
| Merge inactive bytes from src after gf2p8affineinvqb. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Imm8 <= 255) | |
| constexpr simd< std::uint8_t, 64, Arch > | native::gf2p8affineinvqb_maskz (predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept |
| Zero inactive bytes after gf2p8affineinvqb. | |
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template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni))) && requires { sizeof(simd<std::uint8_t, 16, Arch>); }) | |
| consteval simd< std::uint8_t, 16, Arch > | native::gf2p8mulb (simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept |
| Evaluate gf2p8mulb at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd <std::uint64_t, 2, Arch>); }) | |
| consteval simd< std::uint8_t, 16, Arch > | native::gf2p8affineqb (simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept |
| Evaluate gf2p8affineqb at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd <std::uint64_t, 2, Arch>); }) | |
| consteval simd< std::uint8_t, 16, Arch > | native::gf2p8affineinvqb (simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept |
| Evaluate gf2p8affineinvqb at compile time when its register storage is available. | |
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template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint8_t, 16, Arch>); }) | |
| consteval simd< std::uint8_t, 16, Arch > | native::gf2p8mulb_mask (simd< std::uint8_t, 16, Arch > src, predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept |
| Evaluate gf2p8mulb_mask at compile time when its register storage is available. | |
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template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint8_t, 16, Arch>); }) | |
| consteval simd< std::uint8_t, 16, Arch > | native::gf2p8mulb_maskz (predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b) noexcept |
| Evaluate gf2p8mulb_maskz at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd<std::uint64_t, 2, Arch>); }) | |
| consteval simd< std::uint8_t, 16, Arch > | native::gf2p8affineqb_mask (simd< std::uint8_t, 16, Arch > src, predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept |
| Evaluate gf2p8affineqb_mask at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd<std::uint64_t, 2, Arch>); }) | |
| consteval simd< std::uint8_t, 16, Arch > | native::gf2p8affineqb_maskz (predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept |
| Evaluate gf2p8affineqb_maskz at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd<std::uint64_t, 2, Arch>); }) | |
| consteval simd< std::uint8_t, 16, Arch > | native::gf2p8affineinvqb_mask (simd< std::uint8_t, 16, Arch > src, predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept |
| Evaluate gf2p8affineinvqb_mask at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 16, Arch>); sizeof(simd<std::uint64_t, 2, Arch>); }) | |
| consteval simd< std::uint8_t, 16, Arch > | native::gf2p8affineinvqb_maskz (predicate< 16, Arch > k, simd< std::uint8_t, 16, Arch > a, simd< std::uint64_t, 2, Arch > matrix) noexcept |
| Evaluate gf2p8affineinvqb_maskz at compile time when its register storage is available. | |
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template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx))) && requires { sizeof(simd<std::uint8_t, 32, Arch>); }) | |
| consteval simd< std::uint8_t, 32, Arch > | native::gf2p8mulb (simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept |
| Evaluate gf2p8mulb at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::uint64_t, 4, Arch>); }) | |
| consteval simd< std::uint8_t, 32, Arch > | native::gf2p8affineqb (simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept |
| Evaluate gf2p8affineqb at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::uint64_t, 4, Arch>); }) | |
| consteval simd< std::uint8_t, 32, Arch > | native::gf2p8affineinvqb (simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept |
| Evaluate gf2p8affineinvqb at compile time when its register storage is available. | |
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template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint8_t, 32, Arch>); }) | |
| consteval simd< std::uint8_t, 32, Arch > | native::gf2p8mulb_mask (simd< std::uint8_t, 32, Arch > src, predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept |
| Evaluate gf2p8mulb_mask at compile time when its register storage is available. | |
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template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && requires { sizeof(simd<std::uint8_t, 32, Arch>); }) | |
| consteval simd< std::uint8_t, 32, Arch > | native::gf2p8mulb_maskz (predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint8_t, 32, Arch > b) noexcept |
| Evaluate gf2p8mulb_maskz at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::uint64_t, 4, Arch>); }) | |
| consteval simd< std::uint8_t, 32, Arch > | native::gf2p8affineqb_mask (simd< std::uint8_t, 32, Arch > src, predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept |
| Evaluate gf2p8affineqb_mask at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::uint64_t, 4, Arch>); }) | |
| consteval simd< std::uint8_t, 32, Arch > | native::gf2p8affineqb_maskz (predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept |
| Evaluate gf2p8affineqb_maskz at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::uint64_t, 4, Arch>); }) | |
| consteval simd< std::uint8_t, 32, Arch > | native::gf2p8affineinvqb_mask (simd< std::uint8_t, 32, Arch > src, predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept |
| Evaluate gf2p8affineinvqb_mask at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw) && Arch.has(x86_feature::avx512vl))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 32, Arch>); sizeof(simd<std::uint64_t, 4, Arch>); }) | |
| consteval simd< std::uint8_t, 32, Arch > | native::gf2p8affineinvqb_maskz (predicate< 32, Arch > k, simd< std::uint8_t, 32, Arch > a, simd< std::uint64_t, 4, Arch > matrix) noexcept |
| Evaluate gf2p8affineinvqb_maskz at compile time when its register storage is available. | |
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template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f))) && requires { sizeof(simd<std::uint8_t, 64, Arch>); }) | |
| consteval simd< std::uint8_t, 64, Arch > | native::gf2p8mulb (simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept |
| Evaluate gf2p8mulb at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f))) && Imm8 <= 255 && requires { sizeof(simd <std::uint8_t, 64, Arch>); sizeof(simd<std::uint64_t, 8, Arch>); }) | |
| consteval simd< std::uint8_t, 64, Arch > | native::gf2p8affineqb (simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept |
| Evaluate gf2p8affineqb at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f))) && Imm8 <= 255 && requires { sizeof(simd <std::uint8_t, 64, Arch>); sizeof(simd<std::uint64_t, 8, Arch>); }) | |
| consteval simd< std::uint8_t, 64, Arch > | native::gf2p8affineinvqb (simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept |
| Evaluate gf2p8affineinvqb at compile time when its register storage is available. | |
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template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw))) && requires { sizeof(simd<std::uint8_t, 64, Arch>); }) | |
| consteval simd< std::uint8_t, 64, Arch > | native::gf2p8mulb_mask (simd< std::uint8_t, 64, Arch > src, predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept |
| Evaluate gf2p8mulb_mask at compile time when its register storage is available. | |
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template<isa< x86 > Arch> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw))) && requires { sizeof(simd<std::uint8_t, 64, Arch>); }) | |
| consteval simd< std::uint8_t, 64, Arch > | native::gf2p8mulb_maskz (predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint8_t, 64, Arch > b) noexcept |
| Evaluate gf2p8mulb_maskz at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 64, Arch>); sizeof(simd<std::uint64_t, 8, Arch>); }) | |
| consteval simd< std::uint8_t, 64, Arch > | native::gf2p8affineqb_mask (simd< std::uint8_t, 64, Arch > src, predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept |
| Evaluate gf2p8affineqb_mask at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 64, Arch>); sizeof(simd<std::uint64_t, 8, Arch>); }) | |
| consteval simd< std::uint8_t, 64, Arch > | native::gf2p8affineqb_maskz (predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept |
| Evaluate gf2p8affineqb_maskz at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 64, Arch>); sizeof(simd<std::uint64_t, 8, Arch>); }) | |
| consteval simd< std::uint8_t, 64, Arch > | native::gf2p8affineinvqb_mask (simd< std::uint8_t, 64, Arch > src, predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept |
| Evaluate gf2p8affineinvqb_mask at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::gfni) && Arch.has(x86_feature::avx512f) && Arch.has(x86_feature::avx512bw))) && Imm8 <= 255 && requires { sizeof(simd<std::uint8_t, 64, Arch>); sizeof(simd<std::uint64_t, 8, Arch>); }) | |
| consteval simd< std::uint8_t, 64, Arch > | native::gf2p8affineinvqb_maskz (predicate< 64, Arch > k, simd< std::uint8_t, 64, Arch > a, simd< std::uint64_t, 8, Arch > matrix) noexcept |
| Evaluate gf2p8affineinvqb_maskz at compile time when its register storage is available. | |
| template<isa< x86 > Arch, class... Args> | |
| void | native::gf2p8mulb (Args...)=delete |
| Reject unsupported signatures, including implicit raw-register conversions. | |
| template<isa< x86 > Arch, unsigned Imm8, class... Args> | |
| void | native::gf2p8affineqb (Args...)=delete |
| Reject unsupported signatures, including implicit raw-register conversions. | |
| template<isa< x86 > Arch, unsigned Imm8, class... Args> | |
| void | native::gf2p8affineinvqb (Args...)=delete |
| Reject unsupported signatures, including implicit raw-register conversions. | |
| template<isa< x86 > Arch, class... Args> | |
| void | native::gf2p8mulb_mask (Args...)=delete |
| Reject unsupported signatures, including implicit raw-register conversions. | |
| template<isa< x86 > Arch, class... Args> | |
| void | native::gf2p8mulb_maskz (Args...)=delete |
| Reject unsupported signatures, including implicit raw-register conversions. | |
| template<isa< x86 > Arch, unsigned Imm8, class... Args> | |
| void | native::gf2p8affineqb_mask (Args...)=delete |
| Reject unsupported signatures, including implicit raw-register conversions. | |
| template<isa< x86 > Arch, unsigned Imm8, class... Args> | |
| void | native::gf2p8affineqb_maskz (Args...)=delete |
| Reject unsupported signatures, including implicit raw-register conversions. | |
| template<isa< x86 > Arch, unsigned Imm8, class... Args> | |
| void | native::gf2p8affineinvqb_mask (Args...)=delete |
| Reject unsupported signatures, including implicit raw-register conversions. | |
| template<isa< x86 > Arch, unsigned Imm8, class... Args> | |
| void | native::gf2p8affineinvqb_maskz (Args...)=delete |
| Reject unsupported signatures, including implicit raw-register conversions. | |
Files | |
| file | src/native.x86.gfni.ccm |