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native 0.0.1
Vectors, masks and wide register packs for C++26
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Exported Modules | |
| module | native.x86.features |
| module | native.simd |
Functions | |
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template<isa< x86 > Arch, unsigned Selector> requires (Arch.has(x86_feature::sha) && Selector < 4) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sha1rnds4 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept |
| Four SHA-1 rounds; Selector in [0,3] selects the function and constant. | |
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template<isa< x86 > Arch, unsigned Selector> requires (!Arch.has(x86_feature::sha) && Selector < 4 && requires { sizeof(simd<std::uint32_t, 4, Arch>); }) | |
| consteval simd< std::uint32_t, 4, Arch > | native::sha1rnds4 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept |
| Evaluate constant operands without SHA. | |
| template<isa< x86 > Arch, unsigned Selector, class... Args> | |
| void | native::sha1rnds4 (Args...)=delete |
| Reject raw registers, mixed tags and unsupported vector shapes. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::sha)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sha1nexte (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept |
| Add the next E value, derived from a, to the high dword of b. | |
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template<isa< x86 > Arch> requires (!Arch.has(x86_feature::sha) && requires { sizeof(simd<std::uint32_t, 4, Arch>); }) | |
| consteval simd< std::uint32_t, 4, Arch > | native::sha1nexte (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept |
| Evaluate constant operands without SHA. | |
| template<isa< x86 > Arch, class... Args> | |
| void | native::sha1nexte (Args...)=delete |
| Reject raw registers, mixed tags and unsupported vector shapes. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::sha)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sha1msg1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept |
| First SHA-1 message-schedule step. | |
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template<isa< x86 > Arch> requires (!Arch.has(x86_feature::sha) && requires { sizeof(simd<std::uint32_t, 4, Arch>); }) | |
| consteval simd< std::uint32_t, 4, Arch > | native::sha1msg1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept |
| Evaluate constant operands without SHA. | |
| template<isa< x86 > Arch, class... Args> | |
| void | native::sha1msg1 (Args...)=delete |
| Reject raw registers, mixed tags and unsupported vector shapes. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::sha)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sha1msg2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept |
| Final SHA-1 message-schedule step. | |
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template<isa< x86 > Arch> requires (!Arch.has(x86_feature::sha) && requires { sizeof(simd<std::uint32_t, 4, Arch>); }) | |
| consteval simd< std::uint32_t, 4, Arch > | native::sha1msg2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept |
| Evaluate constant operands without SHA. | |
| template<isa< x86 > Arch, class... Args> | |
| void | native::sha1msg2 (Args...)=delete |
| Reject raw registers, mixed tags and unsupported vector shapes. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::sha)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sha256rnds2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept |
| Two SHA-256 rounds: a is CDGH, b is ABEF, c contains two message-plus-constant words. | |
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template<isa< x86 > Arch> requires (!Arch.has(x86_feature::sha) && requires { sizeof(simd<std::uint32_t, 4, Arch>); }) | |
| consteval simd< std::uint32_t, 4, Arch > | native::sha256rnds2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept |
| Evaluate constant operands without SHA. | |
| template<isa< x86 > Arch, class... Args> | |
| void | native::sha256rnds2 (Args...)=delete |
| Reject raw registers, mixed tags and unsupported vector shapes. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::sha)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sha256msg1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept |
| First SHA-256 message-schedule step. | |
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template<isa< x86 > Arch> requires (!Arch.has(x86_feature::sha) && requires { sizeof(simd<std::uint32_t, 4, Arch>); }) | |
| consteval simd< std::uint32_t, 4, Arch > | native::sha256msg1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept |
| Evaluate constant operands without SHA. | |
| template<isa< x86 > Arch, class... Args> | |
| void | native::sha256msg1 (Args...)=delete |
| Reject raw registers, mixed tags and unsupported vector shapes. | |
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template<isa< x86 > Arch> requires (Arch.has(x86_feature::sha)) | |
| constexpr simd< std::uint32_t, 4, Arch > | native::sha256msg2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept |
| Final SHA-256 message-schedule step. | |
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template<isa< x86 > Arch> requires (!Arch.has(x86_feature::sha) && requires { sizeof(simd<std::uint32_t, 4, Arch>); }) | |
| consteval simd< std::uint32_t, 4, Arch > | native::sha256msg2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b) noexcept |
| Evaluate constant operands without SHA. | |
| template<isa< x86 > Arch, class... Args> | |
| void | native::sha256msg2 (Args...)=delete |
| Reject raw registers, mixed tags and unsupported vector shapes. | |
Files | |
| file | src/native.x86.sha.ccm |