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native 0.0.1
Vectors, masks and wide register packs for C++26
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Exported Modules | |
| module | native.x86.features |
| module | native.simd |
Functions | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::pclmul) && Arch.has(x86_feature::avx) && Imm8 <= 255) | |
| constexpr simd< std::uint64_t, 2, Arch > | native::vpclmulqdq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept |
| Multiply selected halves of one 128-bit lane using PCLMUL and AVX. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::vpclmulqdq) && Arch.has(x86_feature::avx) && Imm8 <= 255) | |
| constexpr simd< std::uint64_t, 4, Arch > | native::vpclmulqdq (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept |
| Multiply selected halves independently in two 128-bit lanes; AVX suffices. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (Arch.has(x86_feature::vpclmulqdq) && Arch.has(x86_feature::avx512f) && Imm8 <= 255) | |
| constexpr simd< std::uint64_t, 8, Arch > | native::vpclmulqdq (simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept |
| Multiply selected halves independently in four 128-bit lanes; needs AVX512F. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::pclmul) && Arch.has(x86_feature::avx))) && Imm8 <= 255 && requires { sizeof(simd<std::uint64_t, 2, Arch>); }) | |
| consteval simd< std::uint64_t, 2, Arch > | native::vpclmulqdq (simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept |
| Evaluate vpclmulqdq at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::vpclmulqdq) && Arch.has(x86_feature::avx))) && Imm8 <= 255 && requires { sizeof(simd <std::uint64_t, 4, Arch>); }) | |
| consteval simd< std::uint64_t, 4, Arch > | native::vpclmulqdq (simd< std::uint64_t, 4, Arch > a, simd< std::uint64_t, 4, Arch > b) noexcept |
| Evaluate vpclmulqdq at compile time when its register storage is available. | |
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template<isa< x86 > Arch, unsigned Imm8> requires (!((Arch.has(x86_feature::vpclmulqdq) && Arch.has(x86_feature::avx512f))) && Imm8 <= 255 && requires { sizeof(simd <std::uint64_t, 8, Arch>); }) | |
| consteval simd< std::uint64_t, 8, Arch > | native::vpclmulqdq (simd< std::uint64_t, 8, Arch > a, simd< std::uint64_t, 8, Arch > b) noexcept |
| Evaluate vpclmulqdq at compile time when its register storage is available. | |
| template<isa< x86 > Arch, unsigned Imm8, class... Args> | |
| void | native::vpclmulqdq (Args...)=delete |
| Reject unsupported signatures, including implicit raw-register conversions. | |
Files | |
| file | src/native.x86.vpclmul.ccm |