native 0.0.1
Vectors, masks and wide register packs for C++26
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sha.h
1// SPDX-License-Identifier: BSD-2-Clause OR Apache-2.0
2#pragma once
4#include "native/config.h"
5#include "native/attributes.h"
6#include "native/isa.h"
7#include <cstdint>
8#if NATIVE_HOST_NEON
9#include <arm_neon.h>
10#endif
11
12#if NATIVE_HOST_NEON || defined(NATIVE_DOXYGEN)
13namespace native::detail::arm_sha {
14
15 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha1))
17 uint32x4_t sha1c(uint32x4_t abcd, std::uint32_t e, uint32x4_t wk) noexcept {
18 return vsha1cq_u32(abcd, e, wk);
19 }
20
21 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha1))
23 uint32x4_t sha1p(uint32x4_t abcd, std::uint32_t e, uint32x4_t wk) noexcept {
24 return vsha1pq_u32(abcd, e, wk);
25 }
26
27 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha1))
29 uint32x4_t sha1m(uint32x4_t abcd, std::uint32_t e, uint32x4_t wk) noexcept {
30 return vsha1mq_u32(abcd, e, wk);
31 }
32
33 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha1))
35 std::uint32_t sha1h(std::uint32_t a) noexcept {
36 return vsha1h_u32(a);
37 }
38
39 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha1))
41 uint32x4_t sha1su0(uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11) noexcept {
42 return vsha1su0q_u32(w0_3, w4_7, w8_11);
43 }
44
45 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha1))
47 uint32x4_t sha1su1(uint32x4_t partial, uint32x4_t w12_15) noexcept {
48 return vsha1su1q_u32(partial, w12_15);
49 }
50
51 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha2))
53 uint32x4_t sha256h(uint32x4_t abcd, uint32x4_t efgh, uint32x4_t wk) noexcept {
54 return vsha256hq_u32(abcd, efgh, wk);
55 }
56
57 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha2))
59 uint32x4_t sha256h2(uint32x4_t efgh, uint32x4_t abcd, uint32x4_t wk) noexcept {
60 return vsha256h2q_u32(efgh, abcd, wk);
61 }
62
63 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha2))
65 uint32x4_t sha256su0(uint32x4_t w0_3, uint32x4_t w4_7) noexcept {
66 return vsha256su0q_u32(w0_3, w4_7);
67 }
68
69 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha2))
71 uint32x4_t sha256su1(uint32x4_t partial, uint32x4_t w8_11, uint32x4_t w12_15) noexcept {
72 return vsha256su1q_u32(partial, w8_11, w12_15);
73 }
74
75 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha512))
77 uint64x2_t sha512h(uint64x2_t sum, uint64x2_t fg, uint64x2_t de) noexcept {
78 return vsha512hq_u64(sum, fg, de);
79 }
80
81 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha512))
83 uint64x2_t sha512h2(uint64x2_t sum_ab, uint64x2_t c_, uint64x2_t ab) noexcept {
84 return vsha512h2q_u64(sum_ab, c_, ab);
85 }
86
87 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha512))
89 uint64x2_t sha512su0(uint64x2_t w0_1, uint64x2_t w2_) noexcept {
90 return vsha512su0q_u64(w0_1, w2_);
91 }
92
93 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha512))
95 uint64x2_t sha512su1(uint64x2_t partial, uint64x2_t w14_15, uint64x2_t w9_10) noexcept {
96 return vsha512su1q_u64(partial, w14_15, w9_10);
97 }
98
99 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
101 uint8x16_t eor3(uint8x16_t a, uint8x16_t b, uint8x16_t c) noexcept {
102 return veor3q_u8(a, b, c);
103 }
104
105 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
107 uint16x8_t eor3(uint16x8_t a, uint16x8_t b, uint16x8_t c) noexcept {
108 return veor3q_u16(a, b, c);
109 }
110
111 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
113 uint32x4_t eor3(uint32x4_t a, uint32x4_t b, uint32x4_t c) noexcept {
114 return veor3q_u32(a, b, c);
115 }
116
117 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
119 uint64x2_t eor3(uint64x2_t a, uint64x2_t b, uint64x2_t c) noexcept {
120 return veor3q_u64(a, b, c);
121 }
122
123 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
125 int8x16_t eor3(int8x16_t a, int8x16_t b, int8x16_t c) noexcept {
126 return veor3q_s8(a, b, c);
127 }
128
129 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
131 int16x8_t eor3(int16x8_t a, int16x8_t b, int16x8_t c) noexcept {
132 return veor3q_s16(a, b, c);
133 }
134
135 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
137 int32x4_t eor3(int32x4_t a, int32x4_t b, int32x4_t c) noexcept {
138 return veor3q_s32(a, b, c);
139 }
140
141 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
143 int64x2_t eor3(int64x2_t a, int64x2_t b, int64x2_t c) noexcept {
144 return veor3q_s64(a, b, c);
145 }
146
147 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
149 uint8x16_t bcax(uint8x16_t a, uint8x16_t b, uint8x16_t c) noexcept {
150 return vbcaxq_u8(a, b, c);
151 }
152
153 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
155 uint16x8_t bcax(uint16x8_t a, uint16x8_t b, uint16x8_t c) noexcept {
156 return vbcaxq_u16(a, b, c);
157 }
158
159 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
161 uint32x4_t bcax(uint32x4_t a, uint32x4_t b, uint32x4_t c) noexcept {
162 return vbcaxq_u32(a, b, c);
163 }
164
165 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
167 uint64x2_t bcax(uint64x2_t a, uint64x2_t b, uint64x2_t c) noexcept {
168 return vbcaxq_u64(a, b, c);
169 }
170
171 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
173 int8x16_t bcax(int8x16_t a, int8x16_t b, int8x16_t c) noexcept {
174 return vbcaxq_s8(a, b, c);
175 }
176
177 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
179 int16x8_t bcax(int16x8_t a, int16x8_t b, int16x8_t c) noexcept {
180 return vbcaxq_s16(a, b, c);
181 }
182
183 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
185 int32x4_t bcax(int32x4_t a, int32x4_t b, int32x4_t c) noexcept {
186 return vbcaxq_s32(a, b, c);
187 }
188
189 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
191 int64x2_t bcax(int64x2_t a, int64x2_t b, int64x2_t c) noexcept {
192 return vbcaxq_s64(a, b, c);
193 }
194
195 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
197 uint64x2_t rax1(uint64x2_t a, uint64x2_t b) noexcept {
198 return vrax1q_u64(a, b);
199 }
200
201 template<isa<arm> Arch, unsigned Rotate> requires(Arch.has(arm_feature::sha3) && Rotate < 64)
203 uint64x2_t xar(uint64x2_t a, uint64x2_t b) noexcept {
204 return vxarq_u64(a, b, Rotate);
205 }
206
207 // Reject Clang's implicit same-size vector conversions and scalar narrowing.
208 template<isa<arm> Arch, class... T> void sha1c(T...) = delete;
209
210 template<isa<arm> Arch, class... T> void sha1p(T...) = delete;
211
212 template<isa<arm> Arch, class... T> void sha1m(T...) = delete;
213
214 template<isa<arm> Arch, class... T> void sha1h(T...) = delete;
215
216 template<isa<arm> Arch, class... T> void sha1su0(T...) = delete;
217
218 template<isa<arm> Arch, class... T> void sha1su1(T...) = delete;
219
220 template<isa<arm> Arch, class... T> void sha256h(T...) = delete;
221
222 template<isa<arm> Arch, class... T> void sha256h2(T...) = delete;
223
224 template<isa<arm> Arch, class... T> void sha256su0(T...) = delete;
225
226 template<isa<arm> Arch, class... T> void sha256su1(T...) = delete;
227
228 template<isa<arm> Arch, class... T> void sha512h(T...) = delete;
229
230 template<isa<arm> Arch, class... T> void sha512h2(T...) = delete;
231
232 template<isa<arm> Arch, class... T> void sha512su0(T...) = delete;
233
234 template<isa<arm> Arch, class... T> void sha512su1(T...) = delete;
235
236 template<isa<arm> Arch, class... T> void eor3(T...) = delete;
237
238 template<isa<arm> Arch, class... T> void bcax(T...) = delete;
239
240 template<isa<arm> Arch, class... T> void rax1(T...) = delete;
241
242 template<isa<arm> Arch, unsigned Rotate, class... T> void xar(T...) = delete;
243
244}
245#endif
Compiler attributes for host code, with shader-safe shared modifiers.
constexpr std::uint32_t sha1h(std::uint32_t a) noexcept
Rotate a SHA-1 state word right by two bits; Arch defaults to the module baseline.
constexpr simd< std::uint64_t, 2, Arch > xar(simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
Rotate a XOR b right by Rotate bits in each 64-bit lane; Rotate is in [0, 63].
constexpr simd< std::uint64_t, 2, Arch > rax1(simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
Return a XOR rotate_left(b, 1) in each 64-bit lane.
constexpr simd< std::uint32_t, 4, Arch > sha1p(simd< std::uint32_t, 4, Arch > abcd, std::uint32_t e, simd< std::uint32_t, 4, Arch > wk) noexcept
Perform four SHA-1 rounds using parity; wk already includes the round constants.
constexpr simd< std::uint8_t, 16, Arch > eor3(simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b, simd< std::uint8_t, 16, Arch > c) noexcept
Return a XOR b XOR c for every bit.
constexpr simd< std::uint32_t, 4, Arch > sha256su0(simd< std::uint32_t, 4, Arch > w0_3, simd< std::uint32_t, 4, Arch > w4_7) noexcept
Compute the first part of a four-word SHA-256 schedule update.
constexpr simd< std::uint64_t, 2, Arch > sha512h(simd< std::uint64_t, 2, Arch > sum, simd< std::uint64_t, 2, Arch > fg, simd< std::uint64_t, 2, Arch > de) noexcept
Apply SHA512H to prepared round sums and packed f,g and d,e state.
constexpr simd< std::uint64_t, 2, Arch > sha512su1(simd< std::uint64_t, 2, Arch > partial, simd< std::uint64_t, 2, Arch > w14_15, simd< std::uint64_t, 2, Arch > w9_10) noexcept
Finish the two-word SHA-512 schedule update from sha512su0.
constexpr simd< std::uint32_t, 4, Arch > sha1c(simd< std::uint32_t, 4, Arch > abcd, std::uint32_t e, simd< std::uint32_t, 4, Arch > wk) noexcept
Perform four SHA-1 rounds using choice; wk already includes the round constants.
constexpr simd< std::uint32_t, 4, Arch > sha256su1(simd< std::uint32_t, 4, Arch > partial, simd< std::uint32_t, 4, Arch > w8_11, simd< std::uint32_t, 4, Arch > w12_15) noexcept
Finish the four-word SHA-256 schedule update from sha256su0.
constexpr simd< std::uint32_t, 4, Arch > sha1su0(simd< std::uint32_t, 4, Arch > w0_3, simd< std::uint32_t, 4, Arch > w4_7, simd< std::uint32_t, 4, Arch > w8_11) noexcept
Compute the first part of the SHA-1 schedule update for four consecutive words.
constexpr simd< std::uint64_t, 2, Arch > sha512su0(simd< std::uint64_t, 2, Arch > w0_1, simd< std::uint64_t, 2, Arch > w2_) noexcept
Compute the first part of a two-word SHA-512 schedule update.
constexpr simd< std::uint8_t, 16, Arch > bcax(simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b, simd< std::uint8_t, 16, Arch > c) noexcept
Return a XOR (b AND NOT c) for every bit.
constexpr simd< std::uint32_t, 4, Arch > sha1su1(simd< std::uint32_t, 4, Arch > partial, simd< std::uint32_t, 4, Arch > w12_15) noexcept
Finish the four-word SHA-1 schedule update from sha1su0 and words 12 through 15.
constexpr simd< std::uint32_t, 4, Arch > sha1m(simd< std::uint32_t, 4, Arch > abcd, std::uint32_t e, simd< std::uint32_t, 4, Arch > wk) noexcept
Perform four SHA-1 rounds using majority; wk already includes the round constants.
constexpr simd< std::uint32_t, 4, Arch > sha256h(simd< std::uint32_t, 4, Arch > abcd, simd< std::uint32_t, 4, Arch > efgh, simd< std::uint32_t, 4, Arch > wk) noexcept
Return a,b,c,d after four SHA-256 rounds; wk includes round constants.
constexpr simd< std::uint32_t, 4, Arch > sha256h2(simd< std::uint32_t, 4, Arch > efgh, simd< std::uint32_t, 4, Arch > abcd, simd< std::uint32_t, 4, Arch > wk) noexcept
Return e,f,g,h after four SHA-256 rounds; abcd is the state before those rounds.
constexpr simd< std::uint64_t, 2, Arch > sha512h2(simd< std::uint64_t, 2, Arch > sum_ab, simd< std::uint64_t, 2, Arch > c_, simd< std::uint64_t, 2, Arch > ab) noexcept
Apply SHA512H2 to prepared sums, c, and the packed a,b state.
#define native_inline
inline [[always_inline]]
Definition attributes.h:212
#define native_nodiscard
C++17 [[nodiscard]].
Definition attributes.h:189
#define native_const
[[const]] is not const
Definition attributes.h:108
#define native_target(x)
this indicates a required feature set for the current multiversioned function.
Definition attributes.h:476