native 0.0.1
Vectors, masks and wide register packs for C++26
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native.arm.sha.ccm
1// SPDX-License-Identifier: BSD-2-Clause OR Apache-2.0
2module;
3#include "native/isa_import.h"
4#include "native/arm/detail/crypto_constant.h"
5#include "native/arm/sha.h"
6#include "native/targets.h"
7export module native.arm.sha;
8export import native.arm.features;
9export import native.simd;
10#if NATIVE_HOST_NEON || defined(NATIVE_DOXYGEN)
11export namespace native {
25
27 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha1))
29 constexpr simd<std::uint32_t, 4, Arch> sha1c(simd<std::uint32_t, 4, Arch> abcd, std::uint32_t e, simd<std::uint32_t, 4, Arch> wk) noexcept {
30 if consteval { return detail::arm_constant::sha1_rounds<0>(abcd, e, wk); }
31 else {
32 auto result = detail::arm_sha::sha1c<Arch>(__builtin_bit_cast(uint32x4_t, abcd.to_native()), e, __builtin_bit_cast(uint32x4_t, wk.to_native()));
34 }
35 }
36
38 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha1) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
40 return detail::arm_constant::sha1_rounds<0>(abcd, e, wk);
41 }
42
44 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha1))
46 constexpr simd<std::uint32_t, 4, Arch> sha1p(simd<std::uint32_t, 4, Arch> abcd, std::uint32_t e, simd<std::uint32_t, 4, Arch> wk) noexcept {
47 if consteval { return detail::arm_constant::sha1_rounds<1>(abcd, e, wk); }
48 else {
49 auto result = detail::arm_sha::sha1p<Arch>(__builtin_bit_cast(uint32x4_t, abcd.to_native()), e, __builtin_bit_cast(uint32x4_t, wk.to_native()));
51 }
52 }
53
55 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha1) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
57 return detail::arm_constant::sha1_rounds<1>(abcd, e, wk);
58 }
59
61 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha1))
63 constexpr simd<std::uint32_t, 4, Arch> sha1m(simd<std::uint32_t, 4, Arch> abcd, std::uint32_t e, simd<std::uint32_t, 4, Arch> wk) noexcept {
64 if consteval { return detail::arm_constant::sha1_rounds<2>(abcd, e, wk); }
65 else {
66 auto result = detail::arm_sha::sha1m<Arch>(__builtin_bit_cast(uint32x4_t, abcd.to_native()), e, __builtin_bit_cast(uint32x4_t, wk.to_native()));
68 }
69 }
70
72 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha1) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
74 return detail::arm_constant::sha1_rounds<2>(abcd, e, wk);
75 }
76
78 template<isa<arm> Arch=NATIVE_BASELINE> requires(Arch.has(arm_feature::sha1))
80 constexpr std::uint32_t sha1h(std::uint32_t a) noexcept {
81 if consteval { return (a>>2)|(a<<30); }
82 else { return detail::arm_sha::sha1h<Arch>(a); }
83 }
84
86 template<isa<arm> Arch=NATIVE_BASELINE> requires(!Arch.has(arm_feature::sha1))
87 native_nodiscard consteval std::uint32_t sha1h(std::uint32_t a) noexcept {
88 return (a>>2)|(a<<30);
89 }
90
92 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha1))
95 if consteval { return detail::arm_constant::sha1su0(w0_3, w4_7, w8_11); }
96 else {
97 auto result = detail::arm_sha::sha1su0<Arch>(__builtin_bit_cast(uint32x4_t, w0_3.to_native()), __builtin_bit_cast(uint32x4_t, w4_7.to_native()), __builtin_bit_cast(uint32x4_t, w8_11.to_native()));
99 }
100 }
101
103 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha1) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
105 return detail::arm_constant::sha1su0(w0_3, w4_7, w8_11);
106 }
107
109 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha1))
111 constexpr simd<std::uint32_t, 4, Arch> sha1su1(simd<std::uint32_t, 4, Arch> partial, simd<std::uint32_t, 4, Arch> w12_15) noexcept {
112 if consteval { return detail::arm_constant::sha1su1(partial, w12_15); }
113 else {
114 auto result = detail::arm_sha::sha1su1<Arch>(__builtin_bit_cast(uint32x4_t, partial.to_native()), __builtin_bit_cast(uint32x4_t, w12_15.to_native()));
116 }
117 }
118
120 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha1) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
122 return detail::arm_constant::sha1su1(partial, w12_15);
123 }
124
126 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha2))
128 constexpr simd<std::uint32_t, 4, Arch> sha256h(simd<std::uint32_t, 4, Arch> abcd, simd<std::uint32_t, 4, Arch> efgh, simd<std::uint32_t, 4, Arch> wk) noexcept {
129 if consteval { return detail::arm_constant::sha256_rounds<false>(abcd, efgh, wk); }
130 else {
131 auto result = detail::arm_sha::sha256h<Arch>(__builtin_bit_cast(uint32x4_t, abcd.to_native()), __builtin_bit_cast(uint32x4_t, efgh.to_native()), __builtin_bit_cast(uint32x4_t, wk.to_native()));
133 }
134 }
135
137 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha2) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
139 return detail::arm_constant::sha256_rounds<false>(abcd, efgh, wk);
140 }
141
143 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha2))
145 constexpr simd<std::uint32_t, 4, Arch> sha256h2(simd<std::uint32_t, 4, Arch> efgh, simd<std::uint32_t, 4, Arch> abcd, simd<std::uint32_t, 4, Arch> wk) noexcept {
146 if consteval { return detail::arm_constant::sha256_rounds<true>(efgh, abcd, wk); }
147 else {
148 auto result = detail::arm_sha::sha256h2<Arch>(__builtin_bit_cast(uint32x4_t, efgh.to_native()), __builtin_bit_cast(uint32x4_t, abcd.to_native()), __builtin_bit_cast(uint32x4_t, wk.to_native()));
150 }
151 }
152
154 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha2) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
156 return detail::arm_constant::sha256_rounds<true>(efgh, abcd, wk);
157 }
158
160 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha2))
162 constexpr simd<std::uint32_t, 4, Arch> sha256su0(simd<std::uint32_t, 4, Arch> w0_3, simd<std::uint32_t, 4, Arch> w4_7) noexcept {
163 if consteval { return detail::arm_constant::sha256su0(w0_3, w4_7); }
164 else {
165 auto result = detail::arm_sha::sha256su0<Arch>(__builtin_bit_cast(uint32x4_t, w0_3.to_native()), __builtin_bit_cast(uint32x4_t, w4_7.to_native()));
167 }
168 }
169
171 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha2) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
173 return detail::arm_constant::sha256su0(w0_3, w4_7);
174 }
175
177 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha2))
179 constexpr simd<std::uint32_t, 4, Arch> sha256su1(simd<std::uint32_t, 4, Arch> partial, simd<std::uint32_t, 4, Arch> w8_11, simd<std::uint32_t, 4, Arch> w12_15) noexcept {
180 if consteval { return detail::arm_constant::sha256su1(partial, w8_11, w12_15); }
181 else {
182 auto result = detail::arm_sha::sha256su1<Arch>(__builtin_bit_cast(uint32x4_t, partial.to_native()), __builtin_bit_cast(uint32x4_t, w8_11.to_native()), __builtin_bit_cast(uint32x4_t, w12_15.to_native()));
184 }
185 }
186
188 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha2) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
190 return detail::arm_constant::sha256su1(partial, w8_11, w12_15);
191 }
192
194 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha512))
196 constexpr simd<std::uint64_t, 2, Arch> sha512h(simd<std::uint64_t, 2, Arch> sum, simd<std::uint64_t, 2, Arch> fg, simd<std::uint64_t, 2, Arch> de) noexcept {
197 if consteval { return detail::arm_constant::sha512h(sum, fg, de); }
198 else {
199 auto result = detail::arm_sha::sha512h<Arch>(__builtin_bit_cast(uint64x2_t, sum.to_native()), __builtin_bit_cast(uint64x2_t, fg.to_native()), __builtin_bit_cast(uint64x2_t, de.to_native()));
201 }
202 }
203
205 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha512) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
207 return detail::arm_constant::sha512h(sum, fg, de);
208 }
209
211 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha512))
213 constexpr simd<std::uint64_t, 2, Arch> sha512h2(simd<std::uint64_t, 2, Arch> sum_ab, simd<std::uint64_t, 2, Arch> c_, simd<std::uint64_t, 2, Arch> ab) noexcept {
214 if consteval { return detail::arm_constant::sha512h2(sum_ab, c_, ab); }
215 else {
216 auto result = detail::arm_sha::sha512h2<Arch>(__builtin_bit_cast(uint64x2_t, sum_ab.to_native()), __builtin_bit_cast(uint64x2_t, c_.to_native()), __builtin_bit_cast(uint64x2_t, ab.to_native()));
218 }
219 }
220
222 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha512) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
224 return detail::arm_constant::sha512h2(sum_ab, c_, ab);
225 }
226
228 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha512))
230 constexpr simd<std::uint64_t, 2, Arch> sha512su0(simd<std::uint64_t, 2, Arch> w0_1, simd<std::uint64_t, 2, Arch> w2_) noexcept {
231 if consteval { return detail::arm_constant::sha512su0(w0_1, w2_); }
232 else {
233 auto result = detail::arm_sha::sha512su0<Arch>(__builtin_bit_cast(uint64x2_t, w0_1.to_native()), __builtin_bit_cast(uint64x2_t, w2_.to_native()));
235 }
236 }
237
239 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha512) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
241 return detail::arm_constant::sha512su0(w0_1, w2_);
242 }
243
245 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha512))
247 constexpr simd<std::uint64_t, 2, Arch> sha512su1(simd<std::uint64_t, 2, Arch> partial, simd<std::uint64_t, 2, Arch> w14_15, simd<std::uint64_t, 2, Arch> w9_10) noexcept {
248 if consteval { return detail::arm_constant::sha512su1(partial, w14_15, w9_10); }
249 else {
250 auto result = detail::arm_sha::sha512su1<Arch>(__builtin_bit_cast(uint64x2_t, partial.to_native()), __builtin_bit_cast(uint64x2_t, w14_15.to_native()), __builtin_bit_cast(uint64x2_t, w9_10.to_native()));
252 }
253 }
254
256 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha512) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
258 return detail::arm_constant::sha512su1(partial, w14_15, w9_10);
259 }
260
262 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
264 constexpr simd<std::uint8_t, 16, Arch> eor3(simd<std::uint8_t, 16, Arch> a, simd<std::uint8_t, 16, Arch> b, simd<std::uint8_t, 16, Arch> c) noexcept {
265 if consteval { return detail::arm_constant::logical<false>(a, b, c); }
266 else {
267 auto result = detail::arm_sha::eor3<Arch>(__builtin_bit_cast(uint8x16_t, a.to_native()), __builtin_bit_cast(uint8x16_t, b.to_native()), __builtin_bit_cast(uint8x16_t, c.to_native()));
269 }
270 }
271
273 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
275 return detail::arm_constant::logical<false>(a, b, c);
276 }
277
279 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
281 constexpr simd<std::uint16_t, 8, Arch> eor3(simd<std::uint16_t, 8, Arch> a, simd<std::uint16_t, 8, Arch> b, simd<std::uint16_t, 8, Arch> c) noexcept {
282 if consteval { return detail::arm_constant::logical<false>(a, b, c); }
283 else {
284 auto result = detail::arm_sha::eor3<Arch>(__builtin_bit_cast(uint16x8_t, a.to_native()), __builtin_bit_cast(uint16x8_t, b.to_native()), __builtin_bit_cast(uint16x8_t, c.to_native()));
286 }
287 }
288
290 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
292 return detail::arm_constant::logical<false>(a, b, c);
293 }
294
296 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
298 constexpr simd<std::uint32_t, 4, Arch> eor3(simd<std::uint32_t, 4, Arch> a, simd<std::uint32_t, 4, Arch> b, simd<std::uint32_t, 4, Arch> c) noexcept {
299 if consteval { return detail::arm_constant::logical<false>(a, b, c); }
300 else {
301 auto result = detail::arm_sha::eor3<Arch>(__builtin_bit_cast(uint32x4_t, a.to_native()), __builtin_bit_cast(uint32x4_t, b.to_native()), __builtin_bit_cast(uint32x4_t, c.to_native()));
303 }
304 }
305
307 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
309 return detail::arm_constant::logical<false>(a, b, c);
310 }
311
313 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
315 constexpr simd<std::uint64_t, 2, Arch> eor3(simd<std::uint64_t, 2, Arch> a, simd<std::uint64_t, 2, Arch> b, simd<std::uint64_t, 2, Arch> c) noexcept {
316 if consteval { return detail::arm_constant::logical<false>(a, b, c); }
317 else {
318 auto result = detail::arm_sha::eor3<Arch>(__builtin_bit_cast(uint64x2_t, a.to_native()), __builtin_bit_cast(uint64x2_t, b.to_native()), __builtin_bit_cast(uint64x2_t, c.to_native()));
320 }
321 }
322
324 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
326 return detail::arm_constant::logical<false>(a, b, c);
327 }
328
330 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
332 constexpr simd<std::int8_t, 16, Arch> eor3(simd<std::int8_t, 16, Arch> a, simd<std::int8_t, 16, Arch> b, simd<std::int8_t, 16, Arch> c) noexcept {
333 if consteval { return detail::arm_constant::logical<false>(a, b, c); }
334 else {
335 auto result = detail::arm_sha::eor3<Arch>(__builtin_bit_cast(int8x16_t, a.to_native()), __builtin_bit_cast(int8x16_t, b.to_native()), __builtin_bit_cast(int8x16_t, c.to_native()));
337 }
338 }
339
341 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::int8_t, 16, Arch>); })
343 return detail::arm_constant::logical<false>(a, b, c);
344 }
345
347 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
349 constexpr simd<std::int16_t, 8, Arch> eor3(simd<std::int16_t, 8, Arch> a, simd<std::int16_t, 8, Arch> b, simd<std::int16_t, 8, Arch> c) noexcept {
350 if consteval { return detail::arm_constant::logical<false>(a, b, c); }
351 else {
352 auto result = detail::arm_sha::eor3<Arch>(__builtin_bit_cast(int16x8_t, a.to_native()), __builtin_bit_cast(int16x8_t, b.to_native()), __builtin_bit_cast(int16x8_t, c.to_native()));
354 }
355 }
356
358 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::int16_t, 8, Arch>); })
360 return detail::arm_constant::logical<false>(a, b, c);
361 }
362
364 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
366 constexpr simd<std::int32_t, 4, Arch> eor3(simd<std::int32_t, 4, Arch> a, simd<std::int32_t, 4, Arch> b, simd<std::int32_t, 4, Arch> c) noexcept {
367 if consteval { return detail::arm_constant::logical<false>(a, b, c); }
368 else {
369 auto result = detail::arm_sha::eor3<Arch>(__builtin_bit_cast(int32x4_t, a.to_native()), __builtin_bit_cast(int32x4_t, b.to_native()), __builtin_bit_cast(int32x4_t, c.to_native()));
371 }
372 }
373
375 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::int32_t, 4, Arch>); })
377 return detail::arm_constant::logical<false>(a, b, c);
378 }
379
381 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
383 constexpr simd<std::int64_t, 2, Arch> eor3(simd<std::int64_t, 2, Arch> a, simd<std::int64_t, 2, Arch> b, simd<std::int64_t, 2, Arch> c) noexcept {
384 if consteval { return detail::arm_constant::logical<false>(a, b, c); }
385 else {
386 auto result = detail::arm_sha::eor3<Arch>(__builtin_bit_cast(int64x2_t, a.to_native()), __builtin_bit_cast(int64x2_t, b.to_native()), __builtin_bit_cast(int64x2_t, c.to_native()));
388 }
389 }
390
392 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::int64_t, 2, Arch>); })
394 return detail::arm_constant::logical<false>(a, b, c);
395 }
396
398 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
400 constexpr simd<std::uint8_t, 16, Arch> bcax(simd<std::uint8_t, 16, Arch> a, simd<std::uint8_t, 16, Arch> b, simd<std::uint8_t, 16, Arch> c) noexcept {
401 if consteval { return detail::arm_constant::logical<true>(a, b, c); }
402 else {
403 auto result = detail::arm_sha::bcax<Arch>(__builtin_bit_cast(uint8x16_t, a.to_native()), __builtin_bit_cast(uint8x16_t, b.to_native()), __builtin_bit_cast(uint8x16_t, c.to_native()));
405 }
406 }
407
409 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint8_t, 16, Arch>); })
411 return detail::arm_constant::logical<true>(a, b, c);
412 }
413
415 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
417 constexpr simd<std::uint16_t, 8, Arch> bcax(simd<std::uint16_t, 8, Arch> a, simd<std::uint16_t, 8, Arch> b, simd<std::uint16_t, 8, Arch> c) noexcept {
418 if consteval { return detail::arm_constant::logical<true>(a, b, c); }
419 else {
420 auto result = detail::arm_sha::bcax<Arch>(__builtin_bit_cast(uint16x8_t, a.to_native()), __builtin_bit_cast(uint16x8_t, b.to_native()), __builtin_bit_cast(uint16x8_t, c.to_native()));
422 }
423 }
424
426 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint16_t, 8, Arch>); })
428 return detail::arm_constant::logical<true>(a, b, c);
429 }
430
432 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
434 constexpr simd<std::uint32_t, 4, Arch> bcax(simd<std::uint32_t, 4, Arch> a, simd<std::uint32_t, 4, Arch> b, simd<std::uint32_t, 4, Arch> c) noexcept {
435 if consteval { return detail::arm_constant::logical<true>(a, b, c); }
436 else {
437 auto result = detail::arm_sha::bcax<Arch>(__builtin_bit_cast(uint32x4_t, a.to_native()), __builtin_bit_cast(uint32x4_t, b.to_native()), __builtin_bit_cast(uint32x4_t, c.to_native()));
439 }
440 }
441
443 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
445 return detail::arm_constant::logical<true>(a, b, c);
446 }
447
449 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
451 constexpr simd<std::uint64_t, 2, Arch> bcax(simd<std::uint64_t, 2, Arch> a, simd<std::uint64_t, 2, Arch> b, simd<std::uint64_t, 2, Arch> c) noexcept {
452 if consteval { return detail::arm_constant::logical<true>(a, b, c); }
453 else {
454 auto result = detail::arm_sha::bcax<Arch>(__builtin_bit_cast(uint64x2_t, a.to_native()), __builtin_bit_cast(uint64x2_t, b.to_native()), __builtin_bit_cast(uint64x2_t, c.to_native()));
456 }
457 }
458
460 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
462 return detail::arm_constant::logical<true>(a, b, c);
463 }
464
466 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
468 constexpr simd<std::int8_t, 16, Arch> bcax(simd<std::int8_t, 16, Arch> a, simd<std::int8_t, 16, Arch> b, simd<std::int8_t, 16, Arch> c) noexcept {
469 if consteval { return detail::arm_constant::logical<true>(a, b, c); }
470 else {
471 auto result = detail::arm_sha::bcax<Arch>(__builtin_bit_cast(int8x16_t, a.to_native()), __builtin_bit_cast(int8x16_t, b.to_native()), __builtin_bit_cast(int8x16_t, c.to_native()));
473 }
474 }
475
477 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::int8_t, 16, Arch>); })
479 return detail::arm_constant::logical<true>(a, b, c);
480 }
481
483 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
485 constexpr simd<std::int16_t, 8, Arch> bcax(simd<std::int16_t, 8, Arch> a, simd<std::int16_t, 8, Arch> b, simd<std::int16_t, 8, Arch> c) noexcept {
486 if consteval { return detail::arm_constant::logical<true>(a, b, c); }
487 else {
488 auto result = detail::arm_sha::bcax<Arch>(__builtin_bit_cast(int16x8_t, a.to_native()), __builtin_bit_cast(int16x8_t, b.to_native()), __builtin_bit_cast(int16x8_t, c.to_native()));
490 }
491 }
492
494 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::int16_t, 8, Arch>); })
496 return detail::arm_constant::logical<true>(a, b, c);
497 }
498
500 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
502 constexpr simd<std::int32_t, 4, Arch> bcax(simd<std::int32_t, 4, Arch> a, simd<std::int32_t, 4, Arch> b, simd<std::int32_t, 4, Arch> c) noexcept {
503 if consteval { return detail::arm_constant::logical<true>(a, b, c); }
504 else {
505 auto result = detail::arm_sha::bcax<Arch>(__builtin_bit_cast(int32x4_t, a.to_native()), __builtin_bit_cast(int32x4_t, b.to_native()), __builtin_bit_cast(int32x4_t, c.to_native()));
507 }
508 }
509
511 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::int32_t, 4, Arch>); })
513 return detail::arm_constant::logical<true>(a, b, c);
514 }
515
517 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
519 constexpr simd<std::int64_t, 2, Arch> bcax(simd<std::int64_t, 2, Arch> a, simd<std::int64_t, 2, Arch> b, simd<std::int64_t, 2, Arch> c) noexcept {
520 if consteval { return detail::arm_constant::logical<true>(a, b, c); }
521 else {
522 auto result = detail::arm_sha::bcax<Arch>(__builtin_bit_cast(int64x2_t, a.to_native()), __builtin_bit_cast(int64x2_t, b.to_native()), __builtin_bit_cast(int64x2_t, c.to_native()));
524 }
525 }
526
528 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::int64_t, 2, Arch>); })
530 return detail::arm_constant::logical<true>(a, b, c);
531 }
532
534 template<isa<arm> Arch> requires(Arch.has(arm_feature::sha3))
536 constexpr simd<std::uint64_t, 2, Arch> rax1(simd<std::uint64_t, 2, Arch> a, simd<std::uint64_t, 2, Arch> b) noexcept {
537 if consteval { return detail::arm_constant::rax1(a, b); }
538 else {
539 auto result = detail::arm_sha::rax1<Arch>(__builtin_bit_cast(uint64x2_t, a.to_native()), __builtin_bit_cast(uint64x2_t, b.to_native()));
541 }
542 }
543
545 template<isa<arm> Arch> requires(!Arch.has(arm_feature::sha3) && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
547 return detail::arm_constant::rax1(a, b);
548 }
549
551 template<isa<arm> Arch, unsigned Rotate> requires(Arch.has(arm_feature::sha3) && Rotate < 64)
553 constexpr simd<std::uint64_t, 2, Arch> xar(simd<std::uint64_t, 2, Arch> a, simd<std::uint64_t, 2, Arch> b) noexcept {
554 if consteval { return detail::arm_constant::xar<Rotate>(a, b); }
555 else {
556 auto result = detail::arm_sha::xar<Arch, Rotate>(__builtin_bit_cast(uint64x2_t, a.to_native()), __builtin_bit_cast(uint64x2_t, b.to_native()));
558 }
559 }
560
562 template<isa<arm> Arch, unsigned Rotate> requires(!Arch.has(arm_feature::sha3) && Rotate < 64 && requires { sizeof(simd<std::uint64_t, 2, Arch>); })
564 return detail::arm_constant::xar<Rotate>(a, b);
565 }
566
567 // Require exact semantic shapes and a consistent feature tag.
569 template<isa<arm> Arch, class... T> void sha1c(T...) = delete;
570
572 template<isa<arm> Arch, class... T> void sha1p(T...) = delete;
573
575 template<isa<arm> Arch, class... T> void sha1m(T...) = delete;
576
578 template<isa<arm> Arch=NATIVE_BASELINE, class... T> void sha1h(T...) = delete;
579
581 template<isa<arm> Arch, class... T> void sha1su0(T...) = delete;
582
584 template<isa<arm> Arch, class... T> void sha1su1(T...) = delete;
585
587 template<isa<arm> Arch, class... T> void sha256h(T...) = delete;
588
590 template<isa<arm> Arch, class... T> void sha256h2(T...) = delete;
591
593 template<isa<arm> Arch, class... T> void sha256su0(T...) = delete;
594
596 template<isa<arm> Arch, class... T> void sha256su1(T...) = delete;
597
599 template<isa<arm> Arch, class... T> void sha512h(T...) = delete;
600
602 template<isa<arm> Arch, class... T> void sha512h2(T...) = delete;
603
605 template<isa<arm> Arch, class... T> void sha512su0(T...) = delete;
606
608 template<isa<arm> Arch, class... T> void sha512su1(T...) = delete;
609
611 template<isa<arm> Arch, class... T> void eor3(T...) = delete;
612
614 template<isa<arm> Arch, class... T> void bcax(T...) = delete;
615
617 template<isa<arm> Arch, class... T> void rax1(T...) = delete;
618
620 template<isa<arm> Arch, unsigned Rotate, class... T> void xar(T...) = delete;
621
623}
624#endif
constexpr std::uint32_t sha1h(std::uint32_t a) noexcept
Rotate a SHA-1 state word right by two bits; Arch defaults to the module baseline.
constexpr simd< std::uint64_t, 2, Arch > xar(simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
Rotate a XOR b right by Rotate bits in each 64-bit lane; Rotate is in [0, 63].
constexpr simd< std::uint64_t, 2, Arch > rax1(simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
Return a XOR rotate_left(b, 1) in each 64-bit lane.
constexpr simd< std::uint32_t, 4, Arch > sha1p(simd< std::uint32_t, 4, Arch > abcd, std::uint32_t e, simd< std::uint32_t, 4, Arch > wk) noexcept
Perform four SHA-1 rounds using parity; wk already includes the round constants.
constexpr simd< std::uint8_t, 16, Arch > eor3(simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b, simd< std::uint8_t, 16, Arch > c) noexcept
Return a XOR b XOR c for every bit.
constexpr simd< std::uint32_t, 4, Arch > sha256su0(simd< std::uint32_t, 4, Arch > w0_3, simd< std::uint32_t, 4, Arch > w4_7) noexcept
Compute the first part of a four-word SHA-256 schedule update.
constexpr simd< std::uint64_t, 2, Arch > sha512h(simd< std::uint64_t, 2, Arch > sum, simd< std::uint64_t, 2, Arch > fg, simd< std::uint64_t, 2, Arch > de) noexcept
Apply SHA512H to prepared round sums and packed f,g and d,e state.
constexpr simd< std::uint64_t, 2, Arch > sha512su1(simd< std::uint64_t, 2, Arch > partial, simd< std::uint64_t, 2, Arch > w14_15, simd< std::uint64_t, 2, Arch > w9_10) noexcept
Finish the two-word SHA-512 schedule update from sha512su0.
constexpr simd< std::uint32_t, 4, Arch > sha1c(simd< std::uint32_t, 4, Arch > abcd, std::uint32_t e, simd< std::uint32_t, 4, Arch > wk) noexcept
Perform four SHA-1 rounds using choice; wk already includes the round constants.
constexpr simd< std::uint32_t, 4, Arch > sha256su1(simd< std::uint32_t, 4, Arch > partial, simd< std::uint32_t, 4, Arch > w8_11, simd< std::uint32_t, 4, Arch > w12_15) noexcept
Finish the four-word SHA-256 schedule update from sha256su0.
constexpr simd< std::uint32_t, 4, Arch > sha1su0(simd< std::uint32_t, 4, Arch > w0_3, simd< std::uint32_t, 4, Arch > w4_7, simd< std::uint32_t, 4, Arch > w8_11) noexcept
Compute the first part of the SHA-1 schedule update for four consecutive words.
constexpr simd< std::uint64_t, 2, Arch > sha512su0(simd< std::uint64_t, 2, Arch > w0_1, simd< std::uint64_t, 2, Arch > w2_) noexcept
Compute the first part of a two-word SHA-512 schedule update.
constexpr simd< std::uint8_t, 16, Arch > bcax(simd< std::uint8_t, 16, Arch > a, simd< std::uint8_t, 16, Arch > b, simd< std::uint8_t, 16, Arch > c) noexcept
Return a XOR (b AND NOT c) for every bit.
constexpr simd< std::uint32_t, 4, Arch > sha1su1(simd< std::uint32_t, 4, Arch > partial, simd< std::uint32_t, 4, Arch > w12_15) noexcept
Finish the four-word SHA-1 schedule update from sha1su0 and words 12 through 15.
constexpr simd< std::uint32_t, 4, Arch > sha1m(simd< std::uint32_t, 4, Arch > abcd, std::uint32_t e, simd< std::uint32_t, 4, Arch > wk) noexcept
Perform four SHA-1 rounds using majority; wk already includes the round constants.
constexpr simd< std::uint32_t, 4, Arch > sha256h(simd< std::uint32_t, 4, Arch > abcd, simd< std::uint32_t, 4, Arch > efgh, simd< std::uint32_t, 4, Arch > wk) noexcept
Return a,b,c,d after four SHA-256 rounds; wk includes round constants.
constexpr simd< std::uint32_t, 4, Arch > sha256h2(simd< std::uint32_t, 4, Arch > efgh, simd< std::uint32_t, 4, Arch > abcd, simd< std::uint32_t, 4, Arch > wk) noexcept
Return e,f,g,h after four SHA-256 rounds; abcd is the state before those rounds.
constexpr simd< std::uint64_t, 2, Arch > sha512h2(simd< std::uint64_t, 2, Arch > sum_ab, simd< std::uint64_t, 2, Arch > c_, simd< std::uint64_t, 2, Arch > ab) noexcept
Apply SHA512H2 to prepared sums, c, and the packed a,b state.
#define native_inline
inline [[always_inline]]
Definition attributes.h:212
#define native_nodiscard
C++17 [[nodiscard]].
Definition attributes.h:189
#define native_const
[[const]] is not const
Definition attributes.h:108
#define native_target(x)
this indicates a required feature set for the current multiversioned function.
Definition attributes.h:476
Architecture-tagged vectors, register packs and supporting value types. Native arithmetic follows its...
Standard-library adaptations documented here for SIMD value types.
Omitted architecture arguments use the native.simd provider's baseline.