native 0.0.1
Vectors, masks and wide register packs for C++26
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native.arm.sm3 Module Reference

Exported Modules

module  native.arm.features
module  native.simd

Functions

template<isa< arm > Arch>
requires (Arch.has(arm_feature::sm3))
constexpr simd< std::uint32_t, 4, Arch > native::sm3ss1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
 Rotate and add the lane-three inputs; return SS1 in lane three and zero elsewhere.
template<isa< arm > Arch>
requires (!Arch.has(arm_feature::sm3) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch > native::sm3ss1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
 Evaluate constant operands without the SM3 instruction feature.
template<isa< arm > Arch, int Lane>
requires (Arch.has(arm_feature::sm3) && Lane >= 0 && Lane < 4)
constexpr simd< std::uint32_t, 4, Arch > native::sm3tt1a (simd< std::uint32_t, 4, Arch > state, simd< std::uint32_t, 4, Arch > ss1, simd< std::uint32_t, 4, Arch > words) noexcept
template<isa< arm > Arch, int Lane>
requires (!Arch.has(arm_feature::sm3) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch > native::sm3tt1a (simd< std::uint32_t, 4, Arch > state, simd< std::uint32_t, 4, Arch > ss1, simd< std::uint32_t, 4, Arch > words) noexcept
 Evaluate constant operands without the SM3 instruction feature.
template<isa< arm > Arch, int Lane>
requires (Arch.has(arm_feature::sm3) && Lane >= 0 && Lane < 4)
constexpr simd< std::uint32_t, 4, Arch > native::sm3tt1b (simd< std::uint32_t, 4, Arch > state, simd< std::uint32_t, 4, Arch > ss1, simd< std::uint32_t, 4, Arch > words) noexcept
template<isa< arm > Arch, int Lane>
requires (!Arch.has(arm_feature::sm3) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch > native::sm3tt1b (simd< std::uint32_t, 4, Arch > state, simd< std::uint32_t, 4, Arch > ss1, simd< std::uint32_t, 4, Arch > words) noexcept
 Evaluate constant operands without the SM3 instruction feature.
template<isa< arm > Arch, int Lane>
requires (Arch.has(arm_feature::sm3) && Lane >= 0 && Lane < 4)
constexpr simd< std::uint32_t, 4, Arch > native::sm3tt2a (simd< std::uint32_t, 4, Arch > state, simd< std::uint32_t, 4, Arch > ss1, simd< std::uint32_t, 4, Arch > words) noexcept
template<isa< arm > Arch, int Lane>
requires (!Arch.has(arm_feature::sm3) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch > native::sm3tt2a (simd< std::uint32_t, 4, Arch > state, simd< std::uint32_t, 4, Arch > ss1, simd< std::uint32_t, 4, Arch > words) noexcept
 Evaluate constant operands without the SM3 instruction feature.
template<isa< arm > Arch, int Lane>
requires (Arch.has(arm_feature::sm3) && Lane >= 0 && Lane < 4)
constexpr simd< std::uint32_t, 4, Arch > native::sm3tt2b (simd< std::uint32_t, 4, Arch > state, simd< std::uint32_t, 4, Arch > ss1, simd< std::uint32_t, 4, Arch > words) noexcept
template<isa< arm > Arch, int Lane>
requires (!Arch.has(arm_feature::sm3) && Lane >= 0 && Lane < 4 && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch > native::sm3tt2b (simd< std::uint32_t, 4, Arch > state, simd< std::uint32_t, 4, Arch > ss1, simd< std::uint32_t, 4, Arch > words) noexcept
 Evaluate constant operands without the SM3 instruction feature.
template<isa< arm > Arch>
requires (Arch.has(arm_feature::sm3))
constexpr simd< std::uint32_t, 4, Arch > native::sm3partw1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
 Compute the first four-word SM3 message-schedule update, including lane-zero feedback.
template<isa< arm > Arch>
requires (!Arch.has(arm_feature::sm3) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch > native::sm3partw1 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
 Evaluate constant operands without the SM3 instruction feature.
template<isa< arm > Arch>
requires (Arch.has(arm_feature::sm3))
constexpr simd< std::uint32_t, 4, Arch > native::sm3partw2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
 Finish the four-word SM3 schedule update with the remaining XOR and rotation terms.
template<isa< arm > Arch>
requires (!Arch.has(arm_feature::sm3) && requires { sizeof(simd<std::uint32_t, 4, Arch>); })
consteval simd< std::uint32_t, 4, Arch > native::sm3partw2 (simd< std::uint32_t, 4, Arch > a, simd< std::uint32_t, 4, Arch > b, simd< std::uint32_t, 4, Arch > c) noexcept
 Evaluate constant operands without the SM3 instruction feature.

Files

file  src/native.arm.sm3.ccm