native 0.0.1
Vectors, masks and wide register packs for C++26
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native.x86.vpclmul.ccm
1// SPDX-License-Identifier: BSD-2-Clause OR Apache-2.0
2module;
3#include "native/isa_import.h"
4#include "native/x86/vpclmul.h"
5#include "native/x86/integer_constant.h"
6export module native.x86.vpclmul;
7export import native.x86.features;
8export import native.simd;
9// SPDX-License-Identifier: BSD-2-Clause OR Apache-2.0
10#if NATIVE_HOST_X86 || defined(NATIVE_DOXYGEN)
11export namespace native {
27
29 template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::pclmul) &&
30 Arch.has(x86_feature::avx) && Imm8 <= 255)
32 constexpr simd<std::uint64_t, 2, Arch> vpclmulqdq(simd<std::uint64_t, 2, Arch> a, simd<std::uint64_t, 2, Arch> b) noexcept {
33 if consteval { return detail::x86_instruction_constant::carryless<Imm8>(a, b); }
34 else {
35 return simd<std::uint64_t, 2, Arch>::from_native(detail::x86_vpclmul::vpclmulqdq<Arch, Imm8>(a.to_native(), b.to_native()));
36 }
37 }
38
40 template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::vpclmulqdq) &&
41 Arch.has(x86_feature::avx) && Imm8 <= 255)
44 if consteval { return detail::x86_instruction_constant::carryless<Imm8>(a, b); }
45 else {
46 return simd<std::uint64_t, 4, Arch>::from_native(detail::x86_vpclmul::vpclmulqdq<Arch, Imm8>(a.to_native(), b.to_native()));
47 }
48 }
49
51 template<isa<x86> Arch, unsigned Imm8> requires(Arch.has(x86_feature::vpclmulqdq) &&
52 Arch.has(x86_feature::avx512f) && Imm8 <= 255)
55 if consteval { return detail::x86_instruction_constant::carryless<Imm8>(a, b); }
56 else {
57 return simd<std::uint64_t, 8, Arch>::from_native(detail::x86_vpclmul::vpclmulqdq<Arch, Imm8>(a.to_native(), b.to_native()));
58 }
59 }
60
62 template<isa<x86> Arch, unsigned Imm8> requires(!((Arch.has(x86_feature::pclmul) &&
63 Arch.has(x86_feature::avx))) && Imm8 <= 255 &&
64 requires { sizeof(simd<std::uint64_t, 2, Arch>); })
66 return detail::x86_instruction_constant::carryless<Imm8>(a, b);
67 }
68
70 template<isa<x86> Arch, unsigned Imm8> requires(!((Arch.has(x86_feature::vpclmulqdq) &&
71 Arch.has(x86_feature::avx))) && Imm8 <= 255 &&
72 requires { sizeof(simd<std::uint64_t, 4, Arch>); })
74 return detail::x86_instruction_constant::carryless<Imm8>(a, b);
75 }
76
78 template<isa<x86> Arch, unsigned Imm8> requires(!((Arch.has(x86_feature::vpclmulqdq) &&
79 Arch.has(x86_feature::avx512f))) && Imm8 <= 255 &&
80 requires { sizeof(simd<std::uint64_t, 8, Arch>); })
82 return detail::x86_instruction_constant::carryless<Imm8>(a, b);
83 }
84
85 // Reject implicit register conversions, mixed tags and wrong element types.
87 template<isa<x86> Arch, unsigned Imm8, class... Args>
88 void vpclmulqdq(Args...) = delete;
89
91}
92#endif
#define native_inline
inline [[always_inline]]
Definition attributes.h:212
#define native_nodiscard
C++17 [[nodiscard]].
Definition attributes.h:189
#define native_const
[[const]] is not const
Definition attributes.h:108
#define native_target(x)
this indicates a required feature set for the current multiversioned function.
Definition attributes.h:476
constexpr simd< std::uint64_t, 2, Arch > vpclmulqdq(simd< std::uint64_t, 2, Arch > a, simd< std::uint64_t, 2, Arch > b) noexcept
Multiply selected halves of one 128-bit lane using PCLMUL and AVX.
Architecture-tagged vectors, register packs and supporting value types. Native arithmetic follows its...
Standard-library adaptations documented here for SIMD value types.
Omitted architecture arguments use the native.simd provider's baseline.